Georgia Tech, Partners Launch 3-D Consortium
Georgia Tech's Microsystems Packaging Research Center (PRC) plans to launch the global academia/industry 3-D All Silicon System Module (3DASSM) consortium.
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 9/30/2008 6:02:00 AM
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The consortium’s long-term vision is a complete system that will be entirely silicon-based, according to 3DASSM program manager Ritwik Chatterjee. This includes all components, system boards, ICs and the package itself. Initially, the consortium plans to work on projects in five key categories: low-cost through-silicon vias (TSVs) and stack bonding; electrical design and test; packages with fine-line wiring; embedded active and passive components; and system interconnections. More than 20 research projects have been proposed so far.
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| The 3DASSM program’s long-term vision is a complete system that will be entirely silicon-based. |
“Our 3DASSM consortium isn’t limited to merely TSVs and the stacking of ICs,” said Rao Tummala, director of the PRC. “It’s about ultraminiaturization and ultrafunctionality at the lowest-cost, all-system level — in contrast to what’s being done with system-in-package [SiP] at module level and system-on-chip [SoC] at the IC level. We’re developing an all-silicon 3-D system with seamless integration of ICs, packages and boards.” Tummala said he believes the use of a silicon wafer as a board, with seamless integration of ICs, packages and embedded thin-film components, enabled by TSV interconnections, will bring about a disruptive set of system characteristics never seen before.
One of the consortium’s first projects seeks to address the industry problem of high-cost, low-reliability TSVs. Researchers will look at new fabrication methods for high-density, low-cost TSVs, new structures that improve thermomechanical reliability, novel low-cost solder and adhesive stack bonding methods — research that’s expected to result in a 3-D stack bonding test vehicle and a silicon package test vehicle to demonstrate the improved performance, reliability and manufacturability of the technologies developed.
As far as electrical design and test goes, an emphasis is being placed on reaching beyond 3-D, but starts with low-cost 3-D. This includes electrical design and test of TSV, 3-D stack, SiP and ball grid array (BGA) package and wafer system module. Low signal switching noise, novel equalization methods, and EDA tools for electrical and thermal co-design will all be investigated.
In terms of silicon packages for SiPs and BGAs, 3DASSM is focusing on double-sided silicon substrates enabled by TSV, replacing current organic SiP and processor substrates with improved I/Os, wiring, planarity, thermal and electrical performance, reliability and cost.
For the embedded thin-film components, the research focus is on ultrathin micro- to nano-scale embedded active and passive components with improved properties at lower costs than those achieved in silicon and organic substrates.
And in the system interconnections category, the goal is to solve the mismatch challenge between silicon packages and organic boards by a variety of rigid and compliant interconnections.
To ensure a clear path to commercialization once the industry is ready to roll with the technologies developed by 3DASSM, it’s important to bring other research companies and supply chain companies — from TSV to package to systems, and from raw materials to engineered materials to large area materials, and substrates, components and process and design tools — on board, Chatterjee said. He noted that the consortium is seeing strong global industry/supply chain interest.
