Citing High-k Costs, TSMC Plans Dual-Track 28 nm Solutions in 2010
TSMC said it will offer both silicon oxynitride (SiON) and high-k/metal gate solutions at the 28 nm node, with early manufacturing starting early in 2010 for the low-power turbo process and in the first half of 2010 for the high-k enabled high-performance process. At this stage, high-k/metal gate process flows can add thousands of dollars in per-wafer processing costs, experts said.
David Lammers, News Editor -- Semiconductor International, 9/29/2008 5:22:00 AM
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The 28LPT (low-power turbo) process, based on oxynitrides, will enter early manufacturing in the first quarter of 2010, and the 28HP (high-performance) process, with a high-k/metal gate stack, will be ready in the first half of 2010.
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| TSMC plans to begin its 28 nm low-power manufacturing early in 2010. |
For its microprocessor and high-end graphics customers, TSMC will provide a high-k/metal gate process, said John Wei, TSMC’s senior director of advanced technology marketing. Citing cost and active power consumption considerations, he said SiON offers significant advantages for wireless customers compared with high-k/metal gate stacks.
The TSMC announcement comes just a day before a Silicon Valley technology symposium planned for Sept. 30 by the Common Platform partners, including IBM (Armonk, N.Y.), Chartered Semiconductor Manufacturing Ltd. (Singapore), and Samsung Electronics Co. (Seoul, South Korea). The Common Platform partners emphasize an all high-k/metal gate solution at the 32/28 nm generation, arguing that it provides for a simpler overall process than SiON and tighter scaling of the gate length and contacts. The Common Platform partners seek to lure the volume wireless IC customers away from TSMC, the largest foundry by a wide margin.
Though TSMC will make 32 nm chips for select customers, the company is emphasizing the 28 nm generation as its main leading-edge process, Wei said. A full suite of intellectual property and design support is being readied for the 28 nm processes. At the 45 nm generation, TSMC has emphasized a 40 nm suite of process technology and IP.
TSMC, Wei said, “has defined 40 nm as our main platform at the 40/45 generation, so we already moved 1.5 generations, from 65 to 40. Going to 28 nm is one full-node migration. Right now, 45 nm is in volume production, and 40 nm is getting quite a high number of tapeouts. Some 40 nm products are in the pilot verification stage.”
The cost adder for high-k/metal gate remains considerable. “The No. 1 reason we design in such a two-track way is cost,” Wei said. “High-k and metal gate technology is not mature, and it involves a lot of materials and additional processes. With these, the cost adder goes up. Wireless applications, most of the time, are very cost-sensitive. We feel oxynitride still offers a much more effective solution for wireless applications. It is not like CPUs, where Intel can spend quite a few dollars pursuing a very complicated technology.”
He added that yields are a major consideration. “There are a lot of repeatability and maturity problems with high-k/metal gate. We know there are complexities involved. We have to continue to add steps to the process, so high-k/metal gate costs will continue to go up until they reach a mature stage. Oxynitride on the other hand is very predictable, while high-k/metal gate will pose some risks.”
ALD throughput an issue
High-k remains “a huge cost adder,” said Dean Freeman, a semiconductor manufacturing analyst at Gartner Inc. (Stamford,Conn.). While SiON can be deposited quickly in a chemical vapor deposition (CVD) process, high-k requires atomic layer deposition (ALD) tools that are much slower and more expensive, ~$2M each. The metal gate requires sputtering tools, which also are relatively expensive. One or two extra mask layers also are required for a high-k/metal gate process flow, requiring more lithography tools on a high-k line. “Cost is the critical issue” for high-k/metal gate, Freeman said.
Gartner estimates that a processed leading-edge wafer costs ~$7000 at the major foundries now. Experts at the Sematech-sponsored International Symposium on Advanced Gate Stack Technology, being held this week in Austin, Texas, said that high-k/metal gate technology can add several thousand dollars in manufacturing costs. Equipment costs are much higher, but significantly lower yield is the major cost adder, they said.
Jerry Healey, a former manufacturing engineer at Freescale Semiconductor Inc. (Austin) who now operates a consulting business called Threshold Systems (Austin), said while oxynitrides can be deposited quickly in a batch or single-wafer deposition tool, an ALD tool may require 10-20 minutes to deposit a high-k dielectric. A 25-wafer lot can take 10 hours. Even more importantly, Healey said high-k/metal gate “kills the yields” and adds $1500-2000 per wafer. Others said the additional cost is closer to $3000 on average.
With SiON as a mature process, the natural affinity between silicon and SiON is replaced by less well-understood high-k dielectrics that tend to have higher interface traps and other defects. Experts estimate that a SiON process with a 90% yield may compare with an estimated 70% yield for a high-k/metal gate flow at these early stages. “SiO2 is a God-given material, with a natural interface with silicon,” said T.P. Ma, a professor at Yale University. “For high-k, it will be a slow learning curve, and the problems will be hard to overcome.”
For microprocessor vendors, high-k/metal gate offers significant performance and gate leakage advantages that make those cost adders bearable, Ma said. SiON scaling stopped in 2003 at the 1.2 nm thickness, he noted. While strained silicon took up the performance scaling banner then, it also has reached maturity, Ma said. “How much more strain can they do? Already, the strain levels are almost cracking the wafer. Going to high-k offers not only performance advantages, but also improved gate leakage.”
Active power important
TSMC’s Wei argued that for high-end wireless ICs, a previous concern over standby power has been replaced by active power considerations, driven by handsets being used for web browsing, e-mail and video processing. “The high-end chips have new functions, such as Bluetooth, GPS, mobile TV and Internet browsing. People are going to use their cellphones much more, rather than keep them in standby mode most of the time. So active power plays a much more important role.”
Wei argued that SiON can provide a better solution than high-k/metal gate stack. Citing the well-known rule that power depends on the frequency, the capacitance, and a square of the voltage, Wei said that high-k/metal gate reduces gate leakage, “but when it does that, the capacitance goes up, and active power goes up. It is a trade-off between active power and standby leakage. If active power is the main consideration, then oxynitrides have a better position for power-limited applications.”
Experts at the Sematech conference noted that fundamentally, capacitance depends on the electrical oxide thickness (EOT), regardless of what kind of dielectric is used. “With high-k, you can get a thinner EOT, even though it is more expensive to manufacture,” Ma said. “Wireless applications can live with a thicker EOT than microprocessors. For low-power ICs, foundries like TSMC can make them without too much extra overhead.”
Wei said he could not describe whether TSMC’s high-k/metal gate process is a gate-first or gate-last process. Although the basic decisions have been made, the high-k/metal gate process “will be hardened along the way,” Wei said. “Some customers cannot wait, so they will join our R&D development vehicle,” he added, referring to early 28 nm shuttles. The customers who are early 28 nm high-k adopters will tape out different test vehicles that can be tested on the shuttles.
“Our 28 nm high-k/metal gate is not at a very mature stage now,” Wei said. “Our plan is that by the second half of 2009, the technology will reach its maturity stage. Some customers cannot wait; they want to do it early, so we try to accommodate their needs.”
TSMC refers to its leading-edge low-power process as LPT, with the T standing for either turbo or triple-gate oxide, with a dual-gate oxide as a subset. For customers seeking additional performance, Wei said the third transistor on the LPT process delivers better performance than the high-k/metal gate process. “For the third transistor, we try to minimize the cost. We have the mask adder under good control when we add the third oxide level.”
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