Ambitious Plan for N.Y. Packaging Center
A packaging R&D center supported by IBM and New York officials is likely to begin operations soon, even before funding is finalized and construction of the building can begin. Alain Kaloyeros, CEO of the College of Nanoscale Science and Engineering (CNSE) at the University at Albany, said the center will attract a variety of packaging infrastructure companies to the region.
David Lammers, News Editor -- Semiconductor International, 9/23/2008 10:59:00 AM
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| Alain Kaloyeros, CEO of CNSE |
New York officials are still debating where the packaging center will be located, with some officials from the Hudson Valley Economic Development Corp. seeking a location near IBM’s East Fishkill fab, with others arguing for the Albany region just to the north. While packaging research will begin this year, it may be late 2009 before construction of the center’s building can begin. Plans call for the state to invest $50M in a 120,000 ft2 center to be managed and owned by CNSE. IBM will invest $75M. Rensselaer Polytechnic Institute (RPI, Troy, N.Y.) also will be a partner. Long term, officials believe the partnership will create more than 675 jobs in the region.
“We envision a three-phase type of research program,” Kaloyeros said. “In the short term, the focus will be on how to integrate one chip with another chip, starting with hybrid ICs, using 3-D interconnects. Then, the second phase would see off-chip and on-chip become blended into one type of design that would integrate an IC with an optical chip, for example, and then more exotic materials.”
Long term, packaging and I/O technologies might be transformed by biological models. Kaloyeros said the effort will serve a wide swathe of applications. “Besides systems on a chip, we will work on lab-on-a-chip, or sensor-on-a-chip. We are looking for all kinds of exciting applications, all sorts of bio chips and sensors for defense applications.”
Kaloyeros said he remains “very skeptical” that optical interconnects will be used for on-chip interconnects, citing studies showing that for lengths of a centimeter or less “optical doesn’t show any improvement over conventional electrical” interconnects.
The packaging thrust comes as IBM takes its own 3-D through-silicon via (TSV) program to early product manufacturing. Subramanian Iyer, an IBM distinguished engineer, said IBM is testing out its TSV approach on power amplifier ICs made at its Burlington, Vt., fab. The company might bring 3-D interconnects to logic and memory integration sooner than other companies.
“For logic, TSV 3-D interconnects are absolutely on our roadmap,” Iyer said. “The big advantage that we see is that by using TSVs we can do co-designs, making the processor in one technology and the memory in another technology. It is really a fascinating area. We have product plans how to do this, and a roadmap that starts with a 150 µm pitch down to a 10 µm pitch.”
