NEC Electronics Joins Fishkill Alliance
NEC Electronics has joined the IBM-led Fishkill Alliance, with a goal of implementing NEC's automotive microcontrollers and other products on the high-k/metal gate process at 32 nm design rules.
David Lammers, News Editor -- Semiconductor International, 9/11/2008 10:08:00 AM
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NEC becomes the eighth company to participate in the bulk CMOS development alliance, which includes Chartered Semiconductor Manufacturing Ltd. (Singapore), Freescale Semiconductor Inc. (Austin, Texas), Infineon Technologies AG (Neubiberg, Germany), Samsung Electronics Co. (Seoul, South Korea), STMicroelectronics NV (Geneva) and Toshiba Corp. (Tokyo).
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| NEC Electronics becomes the eighth member of the Fishkill Alliance. |
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| Gary Patton, Vice President, IBM |
“If you look at adoption of the new technology, the rate of people moving into 45 has slowed down. Design teams are challenged to keep on a two-year cycle. There are a number of customers skipping the 45/40 node and going straight to 32 nm to get the big density improvement and power/performance advantage of high-k/metal gate.”
NEC and IBM engineers are beginning discussions this week about how the low-power and general-purpose bulk 32 nm processes will align with NEC’s product strategy, which includes automotive-use microcontrollers and other system-on-a-chip (SoC) products.
NEC Electronics will move IP to the Fishkill multi-project wafer (MPW) shuttle to test out 32 nm designs. Patton said the alliance’s goal is to have the low-power version of the 32 nm process in early production by the fourth quarter of 2009, with the general-purpose version coming in the first quarter of 2010.
Also, the two companies agreed that NEC will participate in the IBM-led research alliance, which is focused on 22 nm and beyond technologies, including extreme ultraviolet (EUV) lithography, 3-D interconnects, and other topics. The research alliance conducts much of its work at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, with additional research based at IBM’s Watson Research Lab (Yorktown, N.Y.) and the IBM Almaden lab (San Jose).
NEC will send engineers to Fishkill, N.Y., by early October to begin 32 nm development. “We need a strong product/technology interaction at the very beginning, especially at these advanced nodes. It is important that the process be tuned up, with the right ground rules and back end of the line, so the process delivers the right performance and yield,” Patton said.
“There is no point in doing an oxide version of our 32 nm technology,” he added. “High-k gives us a significant advantage in power/performance and manufacturability. It enables gate length scaling that we couldn’t do in a poly/oxynitride gate stack. One of the big challenges is creating small contacts which remain open and don’t short to the gate. By scaling the gate length, it gives us more room to drop a contact in between the poly gates. That is a big advantage in terms of yield and manufacturability, besides the obvious performance/power advantages.”
By avoiding strain techniques and multiple gate oxides for the logic and SRAM modules, the Fishkill low-power process will be less complex than a non-high-k process, which would need to use strain techniques to meet performance goals, he said.
IBM says that high-k/metal gate provides performance improvements of up to 35% compared with its 45 nm technology at the same operating voltage, with a power savings of 30-50%. Patton also said, “We’ve developed the 32 nm technology ground rules to enable scaling to a 28 nm half-node shrink.”
NEC has a bulk embedded DRAM (eDRAM) module in production, while IBM uses an SOI-based eDRAM for its high-end servers. Patton said the alliance currently does not have a bulk eDRAM module, but one could be developed quickly. “NEC has a lot of expertise in embedded DRAM. They should start to engage with us, starting today,” he said.
Any alliance partner has the option of taking its designs to the foundry partners within the Common Platform, including Chartered and the foundry operations of IBM and Samsung. The Common Platform will hold a technology event Sept. 30 in Santa Clara, Calif., where Patton said the focus will be on “32 nm technology and what it buys customers in terms of yields, performance and design ease. We also will be talking about what is coming down the pike for 15 nm and 22 nm.”
Advance registration for the Common Platform event is running 25% ahead of last year, when ~1500 people attended, he said. “At this point, customers understand how the platform works for multi-sourcing and the foundry engagement model. For this forum, we are moving away from educating people about the platform and emphasizing the technology.”
