Fine-Tuning CMP

With each new technology node, all process windows become progressively smaller, and the window for overpolishing is no exception. Shrinking CDs with correspondingly thinner metal layers and shorter stack heights have been alerting all sectors to rethink traditional chemical mechanical planarization (CMP) chemistries and processes (Fig. 1). Even the size and placement of dummy structures that protect elements on the wafer during polishing are undergoing changes, as variations in the overall density of copper lines in dielectrics have a greater impact on narrow copper lines just tens of nanometers wide.

1. A view of a 300 mm Reflexion CMP tool as slurries are dripped onto the platen and conditioners are applied to the pad. (Source: Rohm and Haas)

The primary changes in CMP are occurring in copper metallization and the barrier steps for interconnects. Up to 65 nm CDs, new slurries were developed for each new technology node while pads remained relatively unchanged. This strategy has been modified in the past few years, as new pad groove configurations have emerged to meet tighter specifications in planarity and defectivity. Also, there is a growing trend to reduce waste in these costly consumables. Developments in slurries, however, have not lagged behind, continuing on a similar path of innovation as new applications put greater demands on all polishing technologies.

An overall trend in slurries shows a shifting balance toward more chemical activity with gentler mechanical action. This has lead to the development of slurries with gentler particles — smaller abrasives that are less likely to scratch narrow lines and low-k dielectrics. However, hybrid particles — combining polymers with traditionally used ceramics — are showing some promise in terms of improved planarity and defectivity.

Ceramics are generally more aggressive, stiffer abrasives that yield higher removal rates, but they also create higher localized pressure at the contact point on a wafer. This is usually the origin of defects. The shape of the particles is, therefore, of greater importance (edgy vs. rounded) depending on the synthesis process of the particles before they enter the slurry. In contrast, polymeric particles are usually much softer, more resilient and round, and will translate the applied polishing pressure in a more gentle, evenly distributed way.

In theory, indicated Jan Vaes, R&D engineer at IMEC (Leuven, Belgium), ceramics with a polymeric shell combine the best of both worlds — a stiff particle that can exert local pressure but without harsh extremities. The potential is for faster polishing rates with improved planarity, but without an increase in defectivity.

Further, advanced copper metallization is requiring slurry suppliers to take a closer look at inhibitors that are typically added to slurries because copper is not a naturally passivating material. The problem is that the dissolution or corroding power appropriate over a wide copper line may have a substantially localized impact on a narrow 80 nm line, leading to catastrophic failure. This has motivated the development of new types of inhibitor systems.

Researchers at Technion University (Haifa, Israel), for instance, are studying the thermodynamics of copper passivation with sorbate anions. IMEC engineers have subsequently added the sorbate to a test slurry and the results have been impressive — lower dishing values after CMP, which suggests the viability of this approach in a manufacturing environment.

In a slightly different vein, methods are being studied to potentially simplify the planarization process while still bringing into play the need for new inhibitors. For instance, a shift toward noble barrier materials like ruthenium may reduce or eliminate the need for a seed layer, thus enabling the direct plating of copper onto the ruthenium barrier. Ruthenium, however, has a larger driving force for galvanic corrosion, therefore it requires more effective or higher concentrations of anodic inhibitors, Vaes said. Suppliers such as Cabot (Aurora, Ill.) have developed novel barrier slurries with additional inhibitors.

Similarly, self-forming barriers may allow for the elimination of a polish step, but without the need for additional chemistries. Under investigation at IMEC, the layers are formed out of a copper alloy by a thermal process, thus creating a dielectric barrier between the dielectric and copper. Here, the need for the classical barrier polish could be rendered obsolete, although the correction of topography after copper polishing would still be required, said Paul Feeney, CMP Fellow at Cabot.

The development of new slurries continues in a variety of approaches, even when looking at the cathodic side of the corrosion reaction, whereby the kinetics of the oxidizer are altered. This is not surprising given the mounting complexity of the planarization process.

Compared with a decade ago, CMP has matured from a process based on empiricism to one backed by knowledge. In this manner, the end user will ultimately have better control and added robustness in terms of repeatability.

Several suppliers are developing pads that alter the material, porosity and, in particular, the groove patterns of the pad. Rohm and Haas (Phoenix) has developed models to acquire a fundamental understanding of how the wafer interacts with the pad and slurry. This has led to new groove configurations that address very specific issues, such as yield enhancement. For example, some pads have grooves that decrease defects on the order of 50%; others correct uniformity profiles in special cases where no other mechanism or tool parameters are available to adjust, said Todd Buley, CMP integration applications engineering manager at Rohm and Haas.

Most CMP equipment drips slurry onto the pad in a continuous flow, but in a less than optimal manner. Slurry is lost because of centrifugal forces of the spinning platen, so it never makes it under the wafer. Using optimal groove design can improve slurry delivery to the leading edge of the wafer, reducing slurry consumption by up to 35% without sacrificing removal rate, defectivity or uniformity performance. This can result in a 20% reduction in the total cost of consumables, Buley said.

Low-k materials present another element that requires particular attention. For pressure-sensitive porous low-k materials and air-gap approaches, increasing the percentage of pad-wafer contact is critical. Historically, the low-k layer has been protected from the harsh CMP environment with a thin oxide layer. Eliminating this layer by directly polishing the copper and barrier metal and stopping on the low-k would be ideal because the lowest possible effective k value can be obtained only if the capping layer is eliminated. However, inadvertent overpolishing would cause surfactants and additives in the slurry to diffuse into the porous material, creating a possible catastrophe. Overpolishing notwithstanding, maintaining structural integrity during the CMP process is the primary concern.

A standard IC1000 pad has a contact area of ~1%. When 3–5 psi of pressure is applied to the wafer, the point-load pressure at any given spot on that wafer can be in the hundreds of psi. Pads have, therefore, been developed to increase the contact area to reduce point-loading stress, and they may significantly reduce defectivity as well, Buley said. But for fragile low-k materials, pressure distribution is critical. However, reducing the amount of stress on the wafer cannot be achieved with new pad configurations alone. Particle volumes in slurries are also being reduced.

Despite the considerable advances in pad and slurry technologies, changes must be made with caution. Presently, many slurries are developed for the IC1000 pad; therefore, when pads made of completely new materials are used, polishing performance may change significantly. The methods used today to gain a greater understanding of the variables controlling rate and defectivity will ultimately be used to develop and introduce new materials into the CMP process.

The Marangoni drying technology is not new to the industy, but it is only now gaining ground. Applied Materials' (Santa Clara, Calif.) CMP systems use Marangoni dry technology, and it is becoming an enabler beyond the 45 nm node for ultralow-k materials, said Lakshmanan Karuppiah, general manager of the CMP division at Applied Materials. Post-CMP cleans typically consist of cleaning with megasonics and brushes and drying with a spin rinse. However, the hydrophobic nature of low-k films can hold water droplets to the surface of the wafer even after a spin rinse/dry cycle. Because virtually all water droplets have some microscopic particulates dissolved in them, organic residues or watermark defects are left behind on the wafer surface. If the residue contains copper that has precipitated out of solution and recrystallized, the remaining watermarks can lead to critical failures.

Applied Materials' Desica cleaning system uses Marangoni drying that takes advantage of surface tension properties and effectively peels water films off of the wafer's surface, removing residue and defects, even from the trenches.

During drying, the cleaned wafer is vertically inserted into a tank of water. As the wafer is slowly removed, isopropyl alcohol is sprayed at the meniscus between wafer and water, reducing the surface tension on the top layer and eliminating the possibility of watermark defects.

Marangoni drying is typically 30–40% faster than spin drying, a decrease from roughly 40 to 25 seconds, adding productivity advantages for both metals and dielectrics, Karuppiah added.

Metrology plays a bigger role as process windows shrink. At the 20 nm node, for example, stack heights are reduced from 300 to 600 nm to 120 or 80 nm for the most advanced applications, a height well below current post-CMP heights that are between 200 and 400 nm. A loss of 100 or 150 nm of copper is not acceptable. The stacks will contain dielectrics with a porosity of perhaps 30% or more, and are only able to withstand pressures of 0.5–0.8 psi with traditional consumables. On-board or in situ metrology tools must be able to track the wafer during CMP, directly measure uniformity and thickness, and provide feedback of the collected information for the next wafer or use real-time feedback to adjust the processing of the current wafer, where the rate may be slowed and the downforce reduced.

Tighter process windows increase the need for uniform planarization from wafer to wafer, within wafer and across different pattern densities and regions in the die, said Cornel Bozdog, standalone optical CD manager at Nova Measuring Instruments (Rehovot, Israel). The measurement and control of local topography also becomes very important.

The current methodology of taking measurements on test structures in scribe lines is not strongly correlating to yield for selected levels, Bozdog noted from customer feedback. This is prompting a greater need for metrology that directly measures devices on the wafer. Systems such as Nova's scatterometry products are based on algorithms that reproduce the optical response from an actual device, provided that the device structure is periodic in any direction. It delivers angstrom-level control of device geometries.

According to Bozdog, the ability to model the full device — from gates to interconnects — is the key enabler to device measurement. "If you can model the device, you can measure," making it possible to directly measure complex layers that contain preexisting topography. For example, an oxide step in an interconnect CMP process where the barrier removal is strongly dependent on local topography, as well as the topography of the previous interconnect layer underneath, can only be accounted for by direct measurement.

With layers becoming increasingly thinner, one method being investigated for controlling the average remaining thickness is in situ optical endpoint at both film layer transitions and in-film thickness targets. The advantage is that it takes place during the process in real time and with that comes the ability to instantly feed back information. However, some think there are several disadvantages; for example, relatively poor accuracy of tens of angstroms and an inability to differentiate between various structures and feature densities. Although the in situ optical technique is targeted to global wafer-level endpoint and does not directly address growing local planarization issues, it can enable various processing strategies for improvement, Karuppiah noted.

Control at the "local" level can be accomplished with direct measurement, enabling the control of within-wafer non-uniformities. While the measurements are not taken in real time, testing takes place as the wafer is retrieved from the polisher, before it returns to the FOUP; and is designed to match or exceed the throughput of the process tool.

In situ optical process control can be very effective depending on where the sensors are positioned, Karuppiah indicated. By placing in situ sensors behind a window on the polishing pad, the wafer is monitored in real time while polishing. In this manner, changes in pressure or speed can be made to maintain the polishing rate as the pad wears.

At 32 nm CDs, global planarity requirements become stringent, calling for tighter within-wafer and wafer-to-wafer uniformity control. There are basically two techniques that appear to be successful in achieving uniformity. In the past two years, advanced end-point focus control has been shown to be effective for applications stopping inside a film, as an interlevel dielectric (ILD) does, or stopping on a different material (i.e., shallow trench isolation [STI]).

Integrated scatterometry systems measure the remaining within-wafer and wafer-to-wafer thickness profiles with angstrom-level accuracy immediately after the process as the wafer is being transferred back to the FOUP, allowing for next-wafer tuning of the process. For example, with a single measurement recipe in front-end-of-line (FEOL) applications, angstrom-level oxide residues are typically detected across-wafer and across-die for multiple STI structures. For back-end-of-line (BEOL), a single measurement recipe measures copper line thickness profiles across-wafer and across-die for different metal densities.

"The biggest challenge for the consumable supplier is cost reduction," Buley said. With the transition from 65 to 45 nm and below, the industry began targeting a 25% decrease in cost over the previous node with performance goals in tact. The result has been a change in the procurement cycle — a shift, in part, in cost reduction responsibilities from manufacturing to R&D. Working at the development stage has its advantages, one being acquiring a much-needed understanding of the planarization process that, when passed on to manufacturing, produces a more robust process that minimizes fab support costs.

This is just one component. For the chipmaker, a product that is late to market because a process is not ready can be a make or break situation, so managing cost from a supply chain perspective becomes imperative.

In the CMP sector, where costs and complexity are on the rise, the emergence of companies such as Entrepix (Tempe, Ariz.), organizations that serve as a form of outsourcing to fill the gaps in the supply chain, has become an option. With an equipment division and cleanroom facility that can process virtually any wafer size, Entrepix can support any stage of development, from early prototyping up through and including volume production, said CTO Rob Rhoades. It is also possible to apply upgrades, such as a new pad conditioner or an improved polishing head, to existing tools and develop a process that will go with it to ultimately improve performance and financial returns.

Formed in response to requests from highly competitive semiconductor device manufacturers, "We answered the needs of fabs to run lean and still keep pace with aggressive product timelines by accelerating time to revenue and reducing cost and risk," Rhoades said. In the current environment, this is welcome assistance for small and well-established chipmakers alike.

"Changes in technology drive new needs," Feeney noted. And, true to form, each progressive technology node opens the door to new structures and materials. This applies to interconnects, but also increasingly to transistor formation and other new areas. In planarization, the requirements may be somewhat changed, but they are within reach for new applications, such as in 3-D integration schemes, where chips are stacked to enhance density and functionality.

For 3-D integration (Fig. 2), copper-filled nails or posts 5 µm in diameter and 50 µm deep can be used to connect layered chips. The copper is exposed on the backside of each layer when the wafer, glued to a carrier, is thinned to between 20 and 40 µm. Similar to existing processes, an isolation dielectric and barrier metal are deposited before the copper fill. Each layer requires CMP. The difference is in a very thick overburden of 2 to 5 µm, as opposed to 600 or 1000 nm. The 10× thicker copper layer may entail 10× faster planarization rates to achieve an affordable process.

2. This schematic is an example of a layering scheme and some advantages in making 3-D devices a reality. (Source: IMEC)

Feasibility has been demonstrated by stacking up to three dies, Vaes said, with planarization within the tight parameters that were achieved by extending existing processes. However, Vaes noted, the bottlenecks are clear — CMP is an order of magnitude too long and the process is too expensive.

Speed and control are issues with MEMS as well. IMEC is setting up a platform based on polycrystalline silicon germanium (SiGe) devices that are processed on top of existing baseline CMOS chips. Therefore, the same wafer contains the steering and logic needed to actuate the MEMS, which resides on top (Fig. 3). While existing oxide and metal processes are used, ensuring good planarity and selectivity for a given composition of silicon and germanium, and an entirely different set of structures and sizes in the chip layout requires further developments in CMP.

3. Poly SiGe MEMS structures are formed on top of existing CMOS circuits, which drive the tiny mechanisms. (Source: IMEC)

As with 3-D integration, the solutions rest in faster slurries, tuneable removal selectivities and tailored metrology.

According to Vaes, "The solution to getting the best performance is in adapting the processing." The technologies are already in place, whether stopping on a fragile, porous low-k layer or decreasing defectivity requiring less downforce; changing the slurry and using the latest generation of polishing pads. "It is a matter of getting the right set of processing parameters together with the consumables and post-CMP clean," he added. However, making this production-worthy and cost-effective is another matter.