Self-Aligned Double Patterning Gains NAND Flash Favor

Self-aligned double patterning (SADP) is a sidewall spacer transfer patterning technique that is now being adopted at a rate that confirms SADP to be a definitive patterning trend. Within the past year, several NAND flash device makers and industry analysts have indicated that 30 nm devices would likely be made using SADP.^1–3 The nomenclature has not been finalized within the industry and currently goes by several names, including frequency doubling, pitch reduction, spacer mask patterning or SADP. However, they all refer to the same patterning technique, which involves using sidewall spacers to create hard masks as a means of doubling the printed line density. While NAND flash uses these techniques for active area, gate,⁴ word line and bit line, it's projected that DRAM and logic also have opportunities to exploit the patterning technique as designs migrate to more regular layouts.

The strength of spacer mask patterning is in its ability to create high-density arrays of parallel lines with superior linewidth and pitch control. For any given line that is lithographically defined, spacers can be applied on each side that effectively double the line density after stripping the original template material. Depending on the process flow, one can either use the spacers in positive tone to define lines or in negative tone to define trenches (Fig. 1).

1. Depending on the process flow, one can either use the spacers in positive tone to define lines or in negative tone to define trenches.

In both cases, the chip and mask designers need to work closely together because the lines (or trenches) do not necessarily form where the original lithographically generated lines (or trenches) were printed. Secondly, sidewall spacers always form closed-loop bodies and, therefore, need at least one additional cut mask to complete the circuit formation (Fig. 2). This procedure is similar to SRAM formation in current 45 nm logic designs.^5,6

2. This is an example of a two-mask process flow for SRAM-like or gridded design rule consumer logic.8 Litho half-pitch is 44 nm using immersion lithography, and the final structure is 22 nm half-pitch.

Also, the two-mask SADP flow will restrict the designer to either one-line CD with variable space by using the positive-tone process flow, or one-trench CD with variable isolation (line) by using the negative-tone process flow. This restriction stems from the fact that the spacer-defined features all have the same CD set globally by the spacer deposition process, while the contrasting features (core and gap, see Fig. 1) are defined by the resist-line CD (variable) and pitch (variable), respectively.

If designers need to have variable CD on both lines and spaces (L/S), then a third mask is generally implemented (Fig. 3). To avoid the need for three masks, designers are encouraged to use single CD designs,^6,7 and process integration is working to develop a two-mask sequence that enables both variable line and variable space CD. In the latter case, we have recently made progress in demonstrating a selective dry strip process that enables the template to be retained on wide lines during the template removal step (Fig. 4). Schemes like this will play a strong role in reducing cost or loosening design restrictions.

3. This is an example of a three-mask process flow for NAND flash-like designs requiring contact landing pads to be integrated into the array. Litho half-pitch is 64 nm using dry lithography, and the final poly gate structure is 32 nm half-pitch.

4. This demonstration of an SADP process flow allows for variable lines and spaces (L/S) without an additional periphery mask. The process relies on ‘core encapsulation’ and selective dry strip processes.

Application demonstration

To demonstrate 32 nm half-pitch SADP (Fig. 5), we designed a stack using APF (a CVD carbon) to function as the template material (150 nm) and a second layer of APF below to function as a hard mask. The APF template is compatible with a wide variety of spacer materials, such as furnace nitride, furnace poly and CVD nitride, and is easily stripped with nearly infinite selectivity via an O₂ ash. The APF template is capped with a thin silicon nitride (30 nm) to assist in etching, which is typical for any APF application. Between the two layers of APF is a CVD oxide etch-stop (40 nm) serving for the APF template etch, nitride spacer etch and APF template strip.

5. Shown through a series of SEMs, this 32 nm SADP process flow forms a 32 nm half-pitch array into silicon oxide.

For lithography, we used ASML's Twinscan XT:1400e dry scanner with 0.93 numerical aperture (NA) and dipole illumination. For 32 nm SADP, we print on a pitch of 128 nm. The linewidth was biased during exposure to 50 nm, slimmed by dry etch to 32 nm, and transferred into the APF template. The photoresist thickness was minimized to ~100 nm to guarantee all resist and bottom antireflective coatings (BARC) would be fully consumed by completion of the APF template etch.

After template etch, the nitride cap and post-etch residues were stripped in a 5 minute hot phosphoric acid dip prior to depositing a 32 nm PECVD nitride sidewall spacer material. If the nitride cap is not stripped, then a large over-etch will be required during the spacer etch step that negatively impacts CD control. After the spacer etch is performed, the APF template is readily stripped by an O₂ ash. Deviations in the process flow are typically made at this point to accommodate cropping and, in some designs, periphery patterning (Figs. 2 and 3), but these are beyond the scope of this paper.

Following the template strip, the spacer is then used as a hard mask to transfer the pattern below into various substrates, using the second (bottom) layer of APF when required by high-aspect-ratio applications. Final CD-SEM analyses show that lines, core space and gap space can generally be maintained well within 10% of target, with line edge roughness (LER) <2 nm.

Using the SADP process flow as described above, we can demonstrate several realistic device applications, such as shallow trench isolation (STI), poly gate and TANOS charge trap flash gates (Fig. 6).

6. The SADP process flow described can demonstrate several realistic device applications, including 32 nm half-pitch STI (left), 30 nm half-pitch poly gate (middle) and 32 nm TANOS charge-trap flash gate (right).

Patterning performance, benchmarking

Comparing the linewidth CD performance of various double patterning techniques to design requirements can often require sophisticated analysis of tolerance stack-up and multiple root-mean-square (RMS) calculations.^9,10 Single patterning is easy to understand. Within an array of lines, there is a single CD distribution on all lines, pitch is fixed (ignoring mask errors) and, therefore, spaces have the same CD standard deviation as the lines. In scanner double patterning, we have two CD distributions for lines (odd and even) and two CD distributions on spaces (odd and even) because of offset differences during overlay.⁹ In SADP, we have a single CD distribution for lines, and two CD distributions on spaces (core and gap) because of offset differences during the photoresist slimming step.^9,10

Designers are not likely to track which circuits are on odd or even L/S. Therefore, for the purpose of benchmarking the performance of a double patterning technique against design requirements or other competing process flows, it is most straightforward to continue using a single integrated 3 for L/S that encompasses both odd and even features. For scanner double patterning, the scanner alignment error would get rolled into the space CD uniformity (CDU, 3), as trim errors would get rolled into the space CDU for SADP. This method of reporting final integrated performance is more objective and meaningful to the designer; therefore, the data presented in the Table includes both odd and even feature error distributions.

We have conducted numerous integrated patterning demonstrations using SADP into several popular semiconductor materials, for both 32 and 22 nm half-pitch.¹¹ The Table should serve as a good indicator of what CD performance can be expected from SADP. Both 32 and 22 nm SADP, process flows follow the same step sequence discussed within this article; the only changes involve layer thicknesses (which scale to maintain aspect ratio) and the scanner (dry vs. wet) used for printing the initial core pattern. All of the demonstrations shown in the Table have been audited either under live demonstration conditions or through sample wafer shipments to customers.

The results of the various SADP demonstrations (Table) show that SADP (positive tone) can generally control line CDU and linewidth roughness (LWR) to within ~5–6% of the target, while space CDU and LWR are slightly greater at ~9% of target. These numbers represent final integrated data sets, and thus include lithography errors as well as CVD, etch contributing errors, effective misalignment errors and odd/even L/S effects. Presumably, if one were using the negative-tone process flow, then spaces would have better CD performance than lines. Thus, selection of the process flow tone would be optimized by the designer's preference to have best CD control on the line vs. space for each application.

SADP demonstrates both the technical merit and customer traction to be considered a new paradigm in patterning that can enable device scaling beyond the capabilities of single-pass photolithography. Among the memory device manufacturers, where cost is absolutely critical, many have selected SADP as their patterning technology for 3x and 2x nodes, indicating that SADP has economic merit as well. For designers willing to consider gridded design rule layout architectures,^6–8 consumer logic may also have a patterning solution down to the 16 nm logic node using available mature process equipment and running in wafer fabs today.