Double Patterning Battles Cost, Complexity

This year's Sokudo Lithography Breakfast Forum focused on the challenges of double patterning. To be sure, double patterning is not without its challenges, but it nonetheless is positioned as the most promising technology for 32 nm patterning, and likely 22 nm as well.

Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 7/17/2008 10:00:00 AM

This year’s Sokudo Lithography Breakfast Forum, held yesterday morning, focused on the challenges of double patterning. To be sure, double patterning is not without its challenges, but it nonetheless is positioned as the most promising technology for 32 nm patterning, and likely 22 nm as well.

Senior AMD Fellow Harry Levinson set the stage for the remainder of the breakfast discussion from suppliers. As he put it, double patterning is indeed double the trouble, but the motivation to take that route is pretty simple. The industry has traditionally scaled to finer linewidths simply by shrinking the wavelength of the lithography source — from arc lamps to 365 nm to 248 nm to the current leading-edge 193 nm ArF source. Shrinking that wavelength further to 157 nm was not ultimately advantageous for the industry, and the big jump to the extreme ultraviolet (EUV) wavelength of 13.4 nm doesn’t look to be happening anytime soon.

According to Senior AMD Fellow Harry Levinson, although double patterning is indeed double the trouble, the motivation for using it is simple.

So the industry generally agrees that double patterning is needed to bridge the gap until the next source wavelength change. “However, it’s going to be very difficult,” Levinson noted. Even with single patterning, parameters such as overlay, CD control and line edge roughness (LER) scale ~0.7× node to node.

Tighter overlay control is key for making double patterning viable, but another considerable concern is cost. Just how much overlay or cost issues there are depends, in part, on the type of double patterning scheme used. Several of the morning’s presenters highlighted the main possibilities. Although there are variations, they are generally considered to be spacer, double patterning (litho-etch-litho-etch) and double exposure (litho-freeze-litho-etch).

Spacer double patterning — called various things, such as self-aligned double patterning by Applied Materials — does not have overlay concerns because it has only one critical exposure, explained Chris Ngai. However, as several speakers pointed out, it does have serious cost issues. If you’re trying to print an SRAM cell, spacer is probably a good way to go, noted ASML’s Bob Socha. But the cost-of-ownership for spacer technology is considerably higher than other double patterning techniques, he said, adding that not all designs can benefit from the spacer technology.

In fact, which double patterning scheme is chosen is a game of trade-offs — particularly between process complexity and materials complexity, Levinson noted. For example, the standard litho-etch-litho-etch scheme uses materials that are readily available today, but it takes a big hit in throughput and process complexity. Litho-freeze-litho-etch, on the other hand, sounds like a great simplifier, allowing the process to stay in the litho tool, but the idea is based on materials that are not yet available.

There seems to be a lot of hope placed on the pattern freezing technique, with several materials suppliers working on solutions. JSR Micro’s Mark Slezak presented the latest on his company’s resist freeze process, including the etch results done at IMEC. JSR Micro has successfully patterned 32 nm logic patterns, as well as contact hole patterns, with its resist freeze process.

Although the freeze process puts more pressure on the materials side, Slezak said, the fewer steps required in patterning can add up to significant cost savings. The idea of the technology is to image the first material, apply a freeze, and then the frozen first resist is put through the subsequent steps. The trick is coming up with a frozen resist that is resistant to subsequent steps.

Besides coming up with the right materials, there is a long list of requirements for the track systems as well, noted Glen Mori of Sokudo. Sokudo has been doing work with AMD and Rohm and Haas, trying to optimize the resists for curing. In some results Mori showed, they were able to optimize the resist and then preserve the first vertical lines well after horizontal lines were laid down and cured on the second layer.