Lithography Picture Looks Pretty Grim for 22 nm
The key questions posed at an afternoon session at SEMICON West were "Lithography for 22 nm: Will We Have a Viable Solution And Will We Be Able to Afford It?" The answer: Apparently not. Well, maybe.
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 7/16/2008 10:00:00 AM
At yesterday afternoon’s session of the Device Scaling TechXPOT, IBM’s Lars Liebman moderated presentations from six speakers, all of which represented different lithography approaches for reaching the 22 nm node. The key questions posed at the session were “Lithography for 22 nm: Will We Have a Viable Solution – And Will We Be Able to Afford It?” The answer: Apparently not. Well, maybe.
As ASML’s Bill Arnold pointed out, it’s difficult to even define what 22 nm is given that each business has a different idea of what it means. For logic, for example, what’s called the 22 nm node typically has a half-pitch of ~40 nm, and shows up around the last half of 2011, he said. Here, double patterning with 193 nm lithography will do the job, since any sort of resolution is unlikely with single exposure. Double patterning includes three common schemes: spacer, litho-etch-litho and litho-freeze-litho. Recently,
AMD’s Bruno La Fontaine took some issue with the title that was chosen for his speech while he was on vacation: “EUV – Science or Science Fiction.” He went instead with “EUV Lithography: The Road to High Volume Manufacturing.” La Fontaine is uniquely positioned to speak about EUV’s viability, given that AMD recently demonstrated EUV lithography in a full semiconductor process flow to fabricate a 45 nm logic device. And according to La Fontaine, the question is not whether or not EUV lithography will be used, but rather when it will be used.
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| AMD’s Bruno La Fontaine contends that it’s not a question of if EUV, but when EUV. |
Another title discrepancy told a bit of a story when Ben Eynon, newly appointed as vice president of semiconductor business development at Molecular Imprints got up to speak about imprint lithography. Although the program listed the subtitle as “Ready for Prime Time?”, Eynon’s title slide omitted the question mark.
Eynon has just recently joined imprint toolmaker Molecular Imprints, but in his view, imprint lithography has the highest resolution capability available today of any lithography technique, and is extensible to the limits of CMOS. On defectivity issues, he pointed out that imprint is actually on a similar trajectory to immersion, and is about 18 months behind where immersion was when it first came out. So he contends that solutions are well within reach.
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| TSMC’s Burn Lin is advocating maskless e-beam lithography these days. |
Rich Brashears of Cadence Design Systems seemed nervous about the prospect that design flows may not evolve as necessary at the 45 and 32 nm nodes, creating a perhaps insurmountable leap to the 22 nm node, where a fundamental change in design flow will be critical.
One of the most promising solutions presented during the session came from Larry Pileggi, a professor at
Before turning the session over to a final panel discussion, Liebman posed a few questions for the audience. Very few people raised their hands when asked if they thought the 22 nm node would continue on a two-year cycle. “We were not able to convince the audience that we have a technology that will keep us on a two-year roadmap,” Liebman said to his panelists.
The final analysis from the audience: Device scaling will slow down, optical lithography will likely continue on until CMOS scaling runs out of steam, and it will require a fundamental change in design flow.
