IMEC Reduces Cost of Double Patterning Lithography
Staff -- Semiconductor International, 7/14/2008 12:56:00 PM
IMEC (Leuven, Belgium), in collaboration with JSR Corp. (Tokyo), realized a simplified process using only one etch step to reduce the cost of double patterning (DP). 32 nm lines/spaces (L/S) were printed with a double exposure/single etch process, effectively freezing the resist after the first exposure. This simplified process paves the way for an industrial takeup of DP for the 32 nm technology node.
DP will be the primary lithography candidate for the 32 nm technology node. But when using two litho and two etch steps, this technique will be expensive and slow. Therefore, IMEC is developing alternative process flows that reduce the cost of ownership (CoO) by eliminating the intermediate etch step and replacing it with a process step in the litho track.
One way to eliminate the extra etch step is through freezing the resist after the first exposure. With this technique, IMEC has demonstrated 32 nm node logic patterning. The freezing material used to reach this result has been developed by JSR Corp. It prevents the resist from expanding (i.e., CD growth) or shrinking. And when the second resist layer is added, the two do not interact. Also, the freezing material is compatible with the lithography hardware.
The step of freezing the resist is done in the litho track. After exposing the first pattern, the resist is coated with the freezing material. Next, the wafer is baked to freeze the resist. The excess freezing material is then removed using a developer. In the following step, a second resist layer is added and the second exposure is done. To prevent the second resist layer solvent from washing away the first resist, the freezing material changes the properties of the first resist layer so that it becomes non-soluble in the second resist layer.
This technique allowed printing 32 nm dense lines using dipole illumination at 1.0 NA. CDU for the 44 nm high-performance lines was excellent (3σ=2.4nm). Moreover, 32 nm node 2-D logic cells, as well as 32 nm dense lines, could be etched into poly. Lines resulting from the first and second lithography step cannot be distinguished, illustrating the good resolution obtained with this technique.
IMEC is currently transferring this process to its newly installed 1.35 NA immersion scanner to explore this solution for sub-32 nm half-pitches (toward the 22 nm node).
