Industry News: RCP, Competing Litho Techniques, Top Semi Suppliers
-- Semiconductor International, 7/1/2008
Freescale Taking RCP to Pilot Production Stage
After six years of development, Freescale Semiconductor Inc. (Austin, Texas) is moving its pioneering redistributed chip packaging (RCP) technology to early commercial production, said Navjot Chhabra, RCP operations manager.
Wafers containing RCP-optimized chips aimed at MP3 players were received at Freescale's Tempe, Ariz., facility in May, to be followed by Freescale-designed ICs for a Japan-based digital camera customer, Chhabra said. After several months of pilot-mode production in Tempe and product certification at the two initial customers, RCP will move to volume production in the first quarter of 2009 at Tempe, where the company has built a 12,000 ft2 RCP production facility with a capacity of ~800,000 units per week.
The approach has passed commercial-grade reliability specs. Over the next two years, the company's plans call for RCP to be used to reduce the size and improve the performance of a wide variety of products, starting with wireless ICs and moving later to high-performance networking chips, digital signal processors (DSPs) and microprocessors.
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| The redistributed chip packaging (RCP) technology will begin volume production in Tempe, Ariz., in 1Q09. The approach attaches die to a 300 mm substrate. |
"Our direction is moving from simply chip design and package assembly to system design and system assembly. We will be moving up the value chain," Chhabra said.
RCP development began in 2002, spurred by expectations that wireless RCP modules could shrink traditional packages by 30% in the X, Y and Z dimensions. Because the RCP approach processes lots consisting of 25 300 mm panels at a time, there also are cost advantages, particularly over ball grid array (BGA) packaging, he said. Conventional BGA packaging uses expensive substrates and gold wires. RCP uses projection aligners and wet etch processes to define I/O connections with 40 μm feature sizes. The approach encapsulates and builds up the I/O connections using "low-tech, assembly-like manufacturing tools," he said.
Phased approachAt its simplest level, RCP replaces a BGA substrate. Freescale plans to move beyond that to a systems focus, combining heterogeneous components into a small substrate or platform. For some of 45 and 32 nm products, the I/O on the die itself will be optimized for RCP rather than brought out to the edge of the die for wire bonding.
With a systems focus, engineers can eliminate certain filters and other passive components, reducing noise and parasitic capacitance.
Phase I is to do single-die RCP assembly for external and internal customers, Chhabra said. Phase II, which he said is about a year away, is to use RCP to assemble a variety of components into a system module. Not all of those components need be RCP packages, he noted.
Stage III is to use die with the I/O optimized for RCP modules.
"The die today are designed for wire bonding, with the I/O all on the periphery. That takes a lot of area. RCP is like flip-chip, with the vias placed right in the center of the die. With RCP, we can design chips with a much smaller die size and get a huge benefit in terms of the front-end cost."
Materials challengesChhabra said the company has overcome significant materials challenges, particularly in identifying the appropriate encapsulant and dielectric materials. "Getting the materials integrated together and passing reliability — people for years have struggled with those issues."
In the RCP approach, several devices are packaged simultaneously. Between 700 and 2000 singulated die are placed active-side-down on a 300 mm substrate using pick-and-place equipment. The epoxy molding compound is deposited and cured, and the substrate is removed. Next, the redistribution process to route power, signal and ground is performed using standard electroplating equipment and non-critical lithography tools. The encapsulant must hold the panel of die motionless so the projection aligner can define the vias during the I/O build-up process. One challenge was finding an encapsulant that would keep the die from moving and that met the required filler, cure and temperature requirements.
Another was developing a dielectric that could withstand the stresses and strains of packaging without cracking. The RCP dielectric must be able to spin-on in a planar form and be photoimageable, with the right features for the 1500-μm-thick layers.
"There are a number of issues that come up with the dielectrics," Chhabra said. "We start out with 80 μm vias and plan to go down to 40 μm vias eventually. Once we have resolved them, we need to be able to cure the dielectric without shrinkage, and we have to make sure there are no thermal expansion issues. Once we build up all the layers, we have got to be able to saw it easily. And the dielectric ends up being the protective layer."
— David Lammers, News EditorCompeting Lithography Technologies Share Heartaches
Wrapping up two days of technology presentations on advanced-node lithography candidates, the panel discussion at the Sematech Litho Forum (Bolton Landing, N.Y.) could have centered on arguing the pros and cons of extreme ultraviolet (EUV) lithography, double patterning, high-index immersion, nanoimprint and maskless e-beam. Instead, much of the debate had to do with the issues that the various techniques have in common — including business models in the face of huge development costs, shared infrastructures and lithography roadmap roadblocks.
A key recurring theme throughout the panel, which was moderated by Mike Lercel, Sematech's director of lithography, was the difficulty to obtain the results needed in many of the leading-edge lithography technologies without more available resources. As posed in the first question to the panelists, leading-edge lithography tool suppliers are typically large, well capitalized companies; given the huge development costs, what business models are needed to enable innovative lithography technologies?
Players in the nanoimprint lithography space, as well as high-index immersion and maskless development, have repeatedly complained about the minuscule amounts of money coming their way for development — particularly in relation to the amount that has been poured into EUV. But rather than make that well-known complaint again, S.V. Sreenivasan, founder and CTO of nanoimprint toolmaker Molecular Imprints Inc. (MII), made reference to the help they're getting from customers such as Toshiba, which has presented results on MII's behalf. "We're also looking at programs with Sematech, and so on," he said. "That really helps on developing processes, getting data on defects, things like that that's very hard for us to do ourselves."
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| Litho Forum survey results show EUV lithography figuring prominently beyond 2012. Listen to the full results in the webcast ‘Litho Forum Survey: EUV by 2016?’ at www.semiconductor.net/webcasts. (Source: Bernie Roman) |
From a tool development perspective, Sreenivasan said, MII is also looking into an approach in which his company would simply supply modules to a larger integrator — like a lens maker supplying lenses to a stepper integrator. Janice Golda, director of lithography capital equipment at Intel Corp., agreed, noting that the arrangement Sreenivasan spoke of would help to enable new platforms. "We heard a number of presentations [at the Litho Forum]; people with innovative ideas for [e-beam] direct write, which I'd like to see end up in a mask writer," she said. "But getting those technologies mated with the platform capabilities is key to bringing those to market."
The key issue for developing any technology is whether there's enough profit to be made; whether it's worthwhile to cover the development costs of the technology, said TSMC's Burn Lin. "Take nanoimprint or maskless or whatever. If it's a good NGL, it will take over the entire generation, and that's a huge market." He added that just one chipmaker adopting a technology could provide a market of almost 2 billion euros ($3.13B) based on a need of 60 tools. "A few companies together is a huge business case."
Freescale's Will Conley pointed to the benefit of working together and sharing costs, such as efforts going on at Albany NanoTech and IMEC. "I can speak on behalf of Freescale, where the amount of money we're paying into it is quite small, and the benefit is quite large," he said. "And so that benefit is not just large to us as a user, but it also can be very large to the equipment companies in general."
Although some of the innovative technologies face technical challenges of their own — such as source power for EUV lithography or high-index lens material development for the next generation of immersion lithography — panelists noted also how much they share in the way of infrastructure concerns. A key concern for double patterning, for example, is overlay, noted IBM's David Medeiros. "And that's certainly an infrastructure element that's going to affect all of the technologies," he said. "So we really need a lot of focus on all of the contributors to the overlay budget — not just the tooling contributions, but also the mask image placement and the process residuals."
Another key focus area for double patterning, Medeiros added, is in data prep volumes and the handling of that data for mask creation. Golda added, "I think mask infrastructure is the one that crosses just about everything here except maskless — in terms of the data prep, data volumes, getting high-productivity writers..." Data volume is less of a concern at this point for EUV lithography, she said, but other pieces of the infrastructure — including mask inspection, overlay, resists and LER — are common to most of the technologies.
Imprint is looking at the pellicle-less mask handling infrastructure, according to Sreenivasan. "We're looking into what's been done for EUV. That certainly will help us; there's some synergy there between what's been done there and what we would need," he said. "But for us to really get down to the defect levels that people would desire, I think really understanding how you would protect your mask through the entire cycle of its usage is very important for us."
Medeiros added, "I think there's also a good opportunity with the advent of nanoimprint and the focus on 1× template making to maybe beef up the infrastructure resources towards photomask making in general — a historically underfunded business."
For high-index immersion lithography, however, "it's all about the LuAG," Conley said. Currently, the uncertainty of the feasibility of LuAG materials for use in high-index lens elements is seen as something of a showstopper, but getting the funding needed to make progress quickly has been difficult. "Well, first thing, you can't have a supplier cancelling the program," Conley quipped, making reference to the announcement made earlier in the day that Nikon was discontinuing its high-index immersion program.
Bryan Rice, immersion lithography program manager at Sematech, pointed to what he saw as a fundamental breakdown in the funding of innovative technologies: "Do you think that the failure of the semiconductor industry as a whole to provide available and affordable solutions is an indictment of the current research environment?" he asked. Although semiconductor revenue is larger than ever, he said, the industry is seeing repeated requests for additional funding "to make relatively modest investments that might potentially make significant improvements." He added, "I'm wondering if we can draw a correlation between the lack of available and affordable solutions and our current strategy as an industry to invest in new technologies."
— Aaron Hand, Executive Editor, Electronic MediaSome Shuffle Among Top Semi Suppliers
IC Insights Inc. (Scottsdale, Ariz.) announced its rankings for the top 20 semiconductor vendors in the first quarter of 2008, with Qualcomm Inc. (San Diego), Broadcom Corp. (Irvine, Calif.) and Japan-based vendors Panasonic (Osaka, Japan, the new name for Matsushita Electric Industrial Inc.) and NEC Corp. (Tokyo) climbing the rankings.
In its May update to The McClean Report, President Bill McClean said cell phone IC supplier Qualcomm boosted first-quarter revenues by 29% year-over-year, jumping four spots to rank as the 10th largest semiconductor supplier.
Broadcom also jumped four positions and is now the 20th largest semiconductor supplier. Panasonic moved to 19th, and NEC edged up two spots to the 13th position.
Nvidia (Santa Clara, Calif.), the second-largest fabless supplier, registered a "blistering" 37% year-over-year increase in sales, McClean said. Nvidia is now in the 18th position in the ranking, up two places from its rank last year.
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— Staff
