300mmPrime: Tackling Detractors of Fab Productivity

This article was originally presented at the 19th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference on May 7, 2008, and is published in the proceedings. It is reprinted here with permission.

Semiconductor manufacturers face significant wafer processing cost challenges in the coming years, and their success is highly dependent on the ability to extract improvements in productivity and efficiency from existing and future fabs. To address the need to eliminate existing productivity detractors and explore productivity improvements to next-generation fabs (NGFs), an advisory group representing 10 ISMI member companies commissioned the ISMI Factory Simulation and Economic Analysis Focus Teams to perform a special study to ascertain if a 50% manufacturing cycle time and 30% processed wafer cost reduction could be achieved relative to today's nominal fab baseline values.

After rigorous examination of 28 factory productivity detractors identified by ISMI member companies and consulting with equipment suppliers, the teams selected four major categories to be evaluated for cycle time and cost impact on factory productivity:

• First wafer delay (FWD)/setup time
• Equipment availability
• Small-lot manufacturing
• Single wafer processing (SWP) for both low-/high-mix business models

The teams then defined scenarios to comprehend the boundaries of fab operating performance, ensuring the results were not based on any specific path or solution. Assumptions for each scenario and sensitivity analysis were based on a combination of practical experiences, professional judgments and educated guesses.

The goal of the simulation work was to report the relative impact on cycle time and tool count for low- and high-mix factories based on changes in factors such as lot size, equipment setup time/FWD, equipment availability and SWP. Baseline models for high-mix factories containing 100 products and low-mix factories containing 15 products were developed, each considered to be representative of today's 300 mm factories and business models. Sensitivity simulations were then completed by varying the values of each factor and comparing the results to the appropriate baseline model. Figure 1 summarizes the low-mix single-factor experiments. FWD and setup time reductions shortened cycle time by up to 9.4% at a constant equipment count of 817 tools. Assuming an improvement in equipment availability of 5% and 10% reduced cycle time even more — up to 14.7% compared with the 300 mm classic baseline. Combination scenarios yielded up to 18% reduction in cycle time caused by a 10% improvement in equipment availability and a 25% reduction in FWD and setup.

1. 18% reductions in cycle time is the result of 10% improvement in equipment availability and 25% reduction in first wafer delay (FWD) and setup.

Simulations were also performed that varied a combination of factors. Each factor had the potential of various levels of improvement: reasonable improvements and extreme improvements. When extreme factor improvements were combined, the result showed additional cycle time improvements. Figure 2 shows that with constant equipment count (i.e., 817 tools), a 10% increase in equipment availability, combined with a 50% FWD and setup-time reduction, could reduce cycle time by 45.4% using a 12 wafer model. With the same equipment count and improvements in FWD, setup and availability in the 25-wafer model, cycle time was reduced by 42.2%.

2. With constant equipment count, a 10% increase in equipment availability, and 50% reduction in FWD and setup time, cycle time was reduced by 45.4% for the 12-wafer model. A similar cycle time reduction (42.2%) results from improvements in FWD, setup and availability using the 25-wafer model.

However, increases in equipment performance translate into underutilized equipment. When we reduce the equipment count from 817 to 714 for the 12-wafer model, comparable cycle time reduction was gained. Improving overall equipment performance requires fewer tools for an equivalent output, while achieving shorter cycle time. An alternative productivity benefit could be derived by increasing capacity with the original toolset and equipment performance improvements previously referenced.

We next performed simulations that combined SWP with a 5% increase in equipment availability and 25% reduction in FWD and setup times (Fig. 3). These simulations assumed that SWP equipment performs at slower processing rates compared with batch equipment. Therefore, an increase in tool count was required to convert to all SWP. With this increase (865 tools) and the combination of equipment improvements, the 12-wafer model reduced cycle time by 54.9%. Employing selective reductions in minimum cascading requirements provided the best overall cycle time reduction of 60.8% (0.707 days per mask layer) for the 12-wafer model.

3. With a low-mix model, a switch to SWP requires more tools but delivers a significant reduction in cycle time.

High-mix factories were assumed to have a different loading strategy than low-mix factories. Instead of having the largest volume of starts mapped to the most advanced and lengthiest technology process flows, as in the low-mix models, high-mix models have the largest volume loaded across older and shorter technology process flows.

The high-mix conversion of wet clean, wet etch and furnaces from batch equipment to SWP resulted in increasing equipment count from 730 to 780 tools (Fig. 4). Implementing equipment improvements by increasing equipment availability by 10% and reducing FWD and setup time by 25%, the original high-mix SWP equipment count of 780 can be maintained while obtaining a 58.4% reduction in cycle time for the 12-wafer model. With the equipment required to convert to all SWP, these equipment improvements reduced cycle time significantly without increasing equipment count above the minimum requirements for SWP. Slightly lower cycle time benefit (55.9%) was achieved using 25-wafer models, with approximately equal queue size requirements in terms of wafers.

4. With a moderate increase in tool count, significant reduction in cycle time is achieved.

The bottom line

The goal of the ISMI economic analysis work was to provide a quantitative cost benefit assessment of 300mmPrime productivity initiatives through in-depth research and comprehensive modeling. In addition, the team was to develop a methodology to assess the economics of both individual and overall solutions for eliminating productivity detractors. The approach ensured ISMI member company confidentiality by establishing surrogate baseline 300 mm wafer processing costs by technology node and product groups developed from external sources.¹ The surrogate 300 mm "classic" factories were selected by region to represent the leading-edge industry production for each product group.² We selected technology nodes using the International Technology Roadmap for Semiconductors (ITRS) for guidance. Starting material value assumptions were developed using a value curve by time derived from historical cost/area.³

The cost modeling assumptions were then correlated with the ISMI factory modeling base assumption, where applicable, and other nominal industry metrics were defined where appropriate. Future wafer processing costs by technology node for both base (ITRS) and accelerated roadmaps were developed by extrapolating historical trends.

All leading-edge products were shown to have a significant future wafer processing cost challenge to address (Fig. 5). These results were driven by greater depreciation costs (52.9–58.2% of the wafer processed cost), and increased equipment capital expense (process: 66.9–68.9%; metrology: 6.2–7.0%; automation: 3.7–3.8%; installation: 7.3–7.6% of depreciation) required by the increased complexity/node (process: 9.4–10.7% and equipment: 8.7–12.4%) projected to realize the technology roadmap.

5. Wafer cost escalation is mostly driven by increasing cost of the equipment and rapid depreciation of these assets.

These baseline costs were then modified to reflect the enabling and implementation cost defined by the factory modeling scenarios for eliminating productivity detractors. The initial step in this process was to define a methodology for establishing the enabling cost for each of the productivity initiatives. Because specific solutions for eliminating the productivity detractors were unknown, a qualitative approach for the estimates was used. The scenarios were first linked to key needs and possible approaches to solutions, and then evaluated considering all aspects of the supply chain based on development effort, enabling time and implementation probability. Relational enabling costs were then assigned to each initiative based on its initial benefit as determined by simulation.

Using input from the static factory model, cost variances for processed wafers were then calculated based on prioritizing the cost benefit from each initiative. Wafer cost vs. cycle time benefits were then determined (Fig. 6).

6. No scenario meets the goals of 50% reduction in cycle time and 30% reduction in processed wafer cost.

No scenario or combination of scenarios met the target of a simultaneous 50% cycle time and 30% wafer cost reduction. In addition, granting that decreasing cycle time may provide an overall enterprise benefit in some business models, most reductions in cycle time drove increased wafer cost. Finally, a processed wafer cost benefit (<10%) could be realized only at the expense of the cycle time benefit when reducing FWD/setup time and increasing tool availability.

Low-mix factory simulation results concluded that cycle time improvements could be obtained by adding equipment. In some cases, cycle time can be reduced with fewer pieces of equipment when combined with significant operational and equipment improvements.

Because of the assumed slower processing rates of SWP tools, significant throughput improvements are needed to reduce the need for additional tools. For the high-mix factory simulation,³ the limited ability of factory operations to cascade wafers diminishes the potential cycle time reductions associated with the same equipment improvements applied to low-mix factories. High-mix results are similar to low mix, but less cycle time benefit is realized because of the product complexity. Small-lot manufacturing simulations for both low- and high-mix business models indicated a greater dependence on equipment improvements to return expected cycle time benefits.

After a comprehensive economic analysis, no scenario or combination of scenarios met the 30% wafer cost reduction target, and while decreasing cycle time may provide benefit in some business models, most reductions in cycle time increase wafer costs. Some overall wafer cost benefit (<10%) can be realized by trade-off with cycle time benefits by reducing FWD/setup time and increasing tool availability. As a consequence of this analysis, the strategic direction for the ISMI programs was formulated to mobilize the industry to address multiple productivity initiatives.