Sematech Reports Progress at VLSI Meeting
At the 2008 Symposium on VLSI Technology, Sematech researchers described progress with gallium arsenide (GaAs) and silicon germanium channels. Though these materials have higher levels of mobility than silicon, the dielectrics present unique deposition and reliability challenges. Also, Sematech and University of Florida researchers presented work on the effect of strain on GaAs devices.
David Lammers, News Editor -- Semiconductor International, 6/23/2008 9:52:00 AM
Sematech (Austin, Texas) researchers said they are making progress with the heterogeneous devices based on III-V and silicon germanium (SiGe) channels. In three papers presented last week at the 2008 Symposium on VLSI Technology in Honolulu, Sematech staffers described strain engineering on gallium arsenide (GaAs) channels and high-k dielectric studies for SiGe transistors.
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| Raj Jammy, Front-End Transistor Program Director, Sematech |
“We are looking at the primary questions, including what kind of gate stack, what kind of epitaxial technology, what kind of strain do we use, how to do contact formation, these kinds of things,” Jammy said.
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| Sematech researchers developed a SiGe channel device with an aggressively scaled sub-1 nm EOT dielectric. |
“The orientation dependency is much more complicated with III-V materials. With the multi-component materials, the orientation of the island of III-V material, either gallium arsenide or indium gallium arsenide, and then how you apply the strain, has a significant influence,” Jammy said, adding that the impact on leakage must also be considered.
The Sematech team included Scott Thompson, a University of Florida (Gainesville, Fla.) professor who has developed a laboratory tool to measure wafers that are bent to create mechanical stress. The study considered the effect of different kinds of stresses on bulk-GaAs test circuits and extracted both nFET and pFET piezo-resistance coefficients from the wafer-bending experiments.
The team concluded that nFETS do not benefit from uniaxial stress, but show enhancements with biaxial tensile stress. “Importantly, PMOS shows large improvement with uniaxial compressive stress, as compared with a silicon device, though the physical origin for this is not yet understood. Hence, strain-enhanced III-V PMOS, along with high-mobility III-V NMOS, show promise for being incorporated as MOSFET channels at the sub-22 nm technology node. Even larger performance improvements with strain could probably be achieved by incorporating these III-V materials in non-planar finFET or tri-gate structures,” Suthram said.
Two other Sematech papers presented at the symposium considered gate stack engineering in SiGe-based transistors. Because silicon transistors with second-generation high-k insulators and metal gate electrodes are seeking an effective oxide thickness (EOT) of <1 nm, the third-generation devices with silicon germanium or germanium channels must also hit the sub-1 nm EOT target, Jammy said.
Finding a good insulator for both the germanium and III-V channels is “a big challenge. Getting the right quality, with a low interfacial trap density, looks promising. We have worked hard to develop high-k’s for silicon, but these devices are different animals. Then we also have to apply that learning to finFETs, which is a completely different paradigm.”
SiGe nFET devices have high defect levels in the interface between the high-k and channel. When the germanium is epitaxially deposited, a thin silicon capping layer is added to terminate the germanium and provide a stable interface. The Sematech researchers discovered that a higher fraction of germanium and a very thin silicon capping layer provided the best results.
“As the thickness of the silicon cap increases, more silicon is consumed as we create the gate dielectric. The interfacial layer of silicon dioxide doubles in thickness, becoming a 40 Å SiO2 layer. With a high-k layer on top of that, we do not get good coupling to the channel because the EOT is too high. So we need to keep the silicon cap thin,” Jammy said.
Jeff Huang, who presented the paper entitled, “Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directly on SiGe and a Method to Enable sub-1 nm EOT," concluded that depositing the dielectric directly on the SiGe channel reduces process and device design complexity associated with the silicon cap approach. “This scaling and performance demonstration paves the way for surface channel SiGe pFETs at the sub-32 nm nodes,” Huang said.
A related paper, with W.Y. Loh as the lead author, considered reliability issues presented by hot carriers in SiGe devices with a high germanium concentration and thin silicon capping layer. Particularly for pFETs, the interface trap density is high and traps can spread out across the bandgap, presenting additional conduction or degradation mechanisms. Jammy said germanium channels have instrinsically higher numbers of defects at the interface, particularly for the nFETs. To improve hot carrier reliability and improve device lifetime, the Sematech team is continuing “to look carefully at the germanium fraction and how that impacts reliability, as well as the silicon cap thickness,” he said.
Thus far, the Sematech front-end program has achieved fast-switching SiGe devices with a subthreshold swing of 73 mV/decade. The insulator has an EOT of 0.91 nm, using hafnium-based dielectrics.
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