SEMICON West 2008 Executive Outlook

Luc Van den hove, Executive Vice President & COO, IMEC

Starting on a positive note, I am confident that the atmosphere at SEMICON West will be upbeat despite the fact that the outlook for the semiconductor industry at the beginning of 2008 was rather gloomy. Our sector is now in a more mature phase, and we cannot always count on a double-digit growth. Moreover, I would not be surprised if the second half of the year turns out to be considerably better.

Having said that, in which areas do I look for action and announcements at SEMICON West?

Intel, Samsung and TSMC recently agreed to cooperate on a transition to 450 mm wafer production, beginning in 2012. I expect, therefore, that there will be a lot of buzz around 450 mm, testifying to the upbeat atmosphere and positive outlook in the industry.

The semiconductor industry is currently taking some important hurdles toward further scaling. I hope to hear some news about improvements and optimizations in those areas.

First, there is extreme ultraviolet (EUV) lithography. Recently, major progress was announced; two fully functioning systems have produced the first devices. Of course, it will take another few years before EUV can be taken into production. In the meantime, for those applications that need extreme scaling and the smallest possible pitch, there is only one solution: double patterning (DP). What we need to see now are simple, cost-friendly techniques that make DP more easily applicable. Examples are spacer lithography or techniques allowing DP with only one etch step.

A second critical area concerns improvements and optimizations of high-k/metal gate, which is needed to implement this technology at the 32 nm node. Here also, the industry is hoping to see more cost-friendly solutions, especially for implementation in foundry processes and for the use of high-k in cost-sensitive DRAM processes.

In the area of packaging, the industry is working on 3-D integration and suitable 3-D design methods. For technological solutions, the direction is toward smaller, denser interconnects and vias, moving toward 3-D stacked ICs. There are many options, and I would expect to see some initiatives toward standardization. Apart for the technological challenges, the IC design will have to follow suit to make the most of the 3-D possibilities that are opening up.

And, of course, there is a lot of action going on in photovoltaics, so we'll probably see some interesting evolutions there, too.

Richard S. Post, CEO, NEXX Systems Inc.

The increasing use of copper pillars for fine-pitch bumping and the development of through-silicon via (TSV) processes for 3-D stacking are driving cost reductions in wafer processing equipment and the materials used for these applications. In the case of copper pillars, the chemistry options commercially available limit the deposition rate that can be used if coplanarity requirements are to be met. Electrochemical deposition of copper for the filling of TSVs accounts for up to 40% of the total wafer processing cost for 3-D applications. Void-free filling of TSVs is required for high-yield implementation of 3-D, and can only be achieved by filling vias at a sufficiently low rate so that seamless voids are formed during the final stages of the fill process. The key to making both of these processes economical lies in the use of equipment that can provide single-wafer performance with the throughput of a batch tool.

There has been much discussion in the industry regarding the use of via-first or via-last TSV technology, but it now appears that via-first will be the primary choice for most applications. Likewise, there has been a lot of discussion about participation of the outsourced semiconductor assembly and test suppliers (OSATs) in 3-D, and it now appears that the processing of the actual TSVs will be done in the fab, and the microbump, wafer thinning and bonding processes (which are more assembly-like) will be done by the OSATs.

The introduction of 3-D technology has blurred the line between where the fabrication of the device ends and the package begins.

Tony Edwards, Vice President & General Manager, Electronics Division, FEI Co.

SEM technology is evolving to deliver better images and data faster. With the advent of extreme high-resolution (XHR) SEM, semiconductor labs will have the resolution and flexibility required to improve process development and process monitoring applications for current and future nodes.

Process development labs need better imaging performance for testing and analyzing new materials and processes for future nodes. Lab managers have struggled to find a solution that provides sub-nm image resolution on large samples, such as cross-sections, in an analytical chamber that facilitates fast sample transfer and high throughput. XHR SEM delivers sub-nm resolution with an accelerating voltage as little as 1 kV on large samples. XHR SEM imaging requires no additional training or operator requirements and no known service or maintenance issues. Labs will combine all historical analytical capabilities with sub-nm SEM imaging at 1-30 kV.

In addition, IC logic manufacturers require high-resolution imaging of 3-D surfaces for many processes at 32 nm and below. As they begin to design in finFET structures, logic manufacturers need to be able to quickly look at material interfaces and profiles to provide process control feedback. XHR SEM provides images at very low kilovolts to minimize the sample interaction volume and, thus, only look at the top surfaces of devices. This application also requires a high-accuracy stage that can tilt and rotate while keeping the area of interest in the field of view. A similar use case for XHR SEM imaging at very low energies is damage-free imaging of sensitive materials, such as resist and dielectrics.

With better imaging performance, quality and throughput for current and future nodes, advanced semiconductor labs can substantially reduce unnecessary delays in process development and control applications. The result is faster time to market and time to volume with enhanced yields.

John P. Byers, President, Asymtek

We see several developments in semiconductor packaging, especially as they relate to automated fluid dispensing in both new and established markets. Most of the developments are being driven by the consumer's desire for increased functionality, increased speed, package size, and/or environmental impact.

Stacked die, MEMs and the transition from wire-bonded devices to flip-chips are being driven by functionality, size and speed. Manufacturers are now challenged with producing products that require smaller volumes of fluid dispensed more accurately. For example, thin laptops, mobile internet devices or multi-featured cell phones are demanding more functionality in the same or smaller product size. We see that our customers are looking for solutions to dispensing smaller amounts more precisely while increasing throughput.

Demand for solar and LED products is rising along with growing environmental concerns. Although solar panel technology has been around for years, manufacturers are looking for solutions that increase volume and decrease costs so that solar energy is not only the right thing to do environmentally, but is also economically feasible. In a similar vein, LEDs have proven technologies and are finding widespread success in many diverse applications. The main challenge for LED manufacturers is to continue the success by ramping production to meet demand.

Gideon Argov, President, CEO & Board Member, Entegris

At SEMICON West this year, we expect to see a focus on improving productivity in fabs and continued discussion about next-generation fab technologies, such as 450 mm wafer processing, extreme ultraviolet (EUV)/immersion lithography technologies, and the integration of 45 nm and smaller processes and equipment. At 45 nm and beyond, sources of contamination gain complexity and intensify productivity challenges even as the purity requirements of materials and equipment are increasing. Although the process environment and materials in a semiconductor fab are generally “clean” by historical industry standards, as lines get smaller, particles and foreign elements in process chemistry, gases, microenvironments and the equipment chambers pose new and greater threats to overall yield. For example, there is an increasing focus on airborne molecular contamination (AMCs) in the fab and microenvironments. These AMCs include moisture and oxygen in wafer and reticle transport equipment, elements that were once somewhat benign to wafer processing quality, but are now significant contributors to wafer defects in the more sensitive 45 nm processing environment. Equipment, subsystem and component suppliers have introduced several solutions to address these problems.

David Lazovsky, CEO, Intermolecular Inc.

Semiconductor companies spend about $1 out of every $6 they take in on R&D and production qualification. Add the expenditures by equipment and materials suppliers, and the combined R&D investment required to keep the semiconductor industry moving forward totals more than $45B annually. R&D spending is increasing at nearly twice the rate of the industry's revenue growth. Clearly this is not a sustainable situation.

The increase in R&D spending correlates directly to IC device complexity, and new materials integration has been one of the primary contributors to semiconductor complexity over the past several device generations. In fact, materials are now a more important driver of device performance than dimensional scaling. While this shift may seem subtle, it was the catalyst for what has been deemed the industry's “R&D crisis” because it effectively disrupted our almost-exclusive reliance on scaling-enabled innovation.

Obviously, the need for experimental data in R&D and qualification has not changed. Experimental data is the only thing that moves ideas into production, and our industry is still trying to generate it with an infrastructure and methodologies based on device scaling. A specific example is the use of high-volume manufacturing process equipment for basic R&D.

Many companies are facing serious economic challenges by applying yesterday's inefficient R&D methods and infrastructure to today's materials integration requirements. Clearly, R&D efficiency and effectiveness must improve as we put the Periodic Table to work with materials-enabled device innovation. The result: We reduce the time and money spent on product development and qualification, and dramatically improve our R&D return on investment.

Jeffrey Spiegelman, CEO, RASIRC

Rising energy prices are driving up the cost of everything including food, transportation and basic materials. Both consumers and producers are affected, putting pressure on the consumer and industrial electronics market. To retain the same share of world GDP, consumer electronics will need to continue to innovate new experiences and, at the same time, give more for the same or less consumer dollars. For the industrial market, semiconductor technology will need to be applied to improve productivity and energy efficiency, and enable the reliance on alternative energy.

These goals will be achieved through semiconductor, nanotechnology and photovoltaic (PV) processes. Long-term energy costs can be stabilized and driven down through a combination of efficiency and renewable energy sources, enabling continued growth of semiconductor and equipment manufacturing, as well as PV devices. Semiconductor equipment manufacturers will increasingly design equipment for higher throughput, lower cost and greater materials efficiency. Both substrates and chemistries, including water, will be affected.

The rapid growth in both volume and efficiency of PV will outpace the pundits' predictions of what percent of energy can be derived to move the world from carbon-based to silicon-based. The recent breakthrough of a carbon nanotube radio demonstrates a 25,000× reduction in the size of a radio transmitter, with a related reduction in power requirements. By blending the technology know-how of the semiconductor equipment industry with the rapidly developing R&D processes in alternative energy and nanotechnology, we can change our energy consumption without returning to the dark ages. We will see very rapid and sustained growth for those companies that develop the equipment, new materials and delivery components needed for these new processes to improve yield and reduce device costs.

Ardy Johnson, Vice President, Marketing, Rudolph Technologies

While current economic conditions are forcing semiconductor manufacturers to limit their capital equipment expenditures, new technologies are driving the purchase of process characterization systems for both the front and back end.

For example, the adoption of immersion lithography is driving demand for wafer-edge inspection capabilities that can detect defects at the vulnerable film edges. The problem is exacerbated by the ease with which the immersion fluid can then transport the defects from the edge to the active area of the wafer surface.

The escalating cost and technical complexity of advanced packaging technologies in the back end is yet another example where continuing investment is being made.

Finally, the development of 3-D ICs will drive the introduction of new technologies and processes throughout the fab, front and back end and, for each new process, there will be new requirements for inspection and metrology. Moreover, it appears now that no one approach is likely to dominate all 3-D IC applications, and a variety of solutions will emerge and persist, further increasing the diversity and complexity of the fab environment. Fab managers, already challenged to manage the huge volume of data generated by an advanced manufacturing operation, will find intelligent automation and analysis capabilities indispensable in future operations.

Linda C. Rae, Executive Vice President & COO, Keithley Instruments

The trend toward higher levels of functional integration (SoC), more low-power mobile applications and increasingly harsh operating environments are driving many of today's test and measurement challenges. This is in addition to the electrical measurement challenges brought on by ongoing CMOS scaling efforts. These trends lead to a significantly increased dependence on electrical characterization throughout the semiconductor lifecycle; as a result, electrical characterization speeds significantly impact cycle times in technology development and process integration.

The concept of “designing in reliability” is coming of age. The industry can no longer depend on “screening for reliability” or adjusting a process to meet reliability needs of harsh operating environments, Rather, every part of the semiconductor development process plays a key role in meeting the consumer's expectations. This means that reliability characteristics must be modeled and monitored throughout materials selection, technology development, process integration and production. In addition, by the nature of the intrinsic failures of the deeply scaled CMOS technologies, larger sample sizes are required for accurate modeling.

The focus on reliability earlier in the semiconductor lifecycle means that technology development labs are taking advantage of every opportunity to shorten characterization cycle times by adopting wafer-level reliability over package level and relying on parallel wafer-level reliability to reduce reliability modeling studies from weeks to days.

Production and yield ramp are strongly influenced by increased randomness of extrinsic defects and intrinsic material and process variations. As a result, there is a need for “better parametric test coverage” to ensure that both local and global parametric variations are accurately characterized and correctly influence process controls to maximize yield and yield ramp.

For example, test engineers have increased the amount of parametric test data used for process monitoring by a factor of 10 over the past 10 years. This rate of growth is accelerating, and the amount of data required may increase by another factor of 10 in the next several years. The semiconductor industry is seeing a rapidly growing need for electrical parameter characterization and monitoring to achieve competitive IC performance without sacrificing yields.

Finally, it is difficult to know what the future holds. With so many new materials, device types and increased mask layers, predicting the measurement needs just a few years out becomes problematic. Recently emerging techniques, such as high-speed pulsing and high-frequency measurements, are being adopted in materials and device development labs. IC manufacturers are looking for measurement tools with flexible architectures that are able to grow into these future needs.

Tom St. Dennis, Senior Vice President & General Manager, Silicon Systems Group, Applied Materials

From our perspective, it's all about scale. In semiconductors, chipmakers are scaling down their devices to create faster, more efficient and more portable consumer electronics. In solar, larger panels are required for the world's largest manufacturing facilities to drive clean energy production to a global scale.

Significant progress has been made in the past year, especially in high-k/metal gate film stacks and self-aligned double patterning. At the show, we'll see solutions that extend gap-fill technology for scaled-down higher aspect-ratio structures and interface engineering technology that achieves higher overall chip yield.

Defect-free photomasks are also a critical concern because one killer defect can render the costly mask useless. Removing particles without damaging the mask has been a challenge, as has defect inspection — because resolution enhancement techniques make the pattern on the mask almost unrecognizable from the pattern that will ultimately appear on the wafer. Recent breakthroughs in these areas have made mask cleaning and inspection processes faster and much more efficient.

Defects on the wafer's edge are also becoming a major source of yield loss, and we see that the emerging field of edge engineering, including edge cleaning and edge defect review, will become increasingly important. We expect new front- and back-end-of-line applications to emerge for both dry and immersion lithographic process flows.

Up and down the industry food chain, new technologies must be commercialized quickly yet robustly, with high levels of quality and the ability to sustain subsequent cost reductions. A wide range of customized service products, including automation, location-independent diagnostic teams and specialized component coating, cleaning and reconditioning can be harnessed to maximize the predictability, efficiency and cost-effectiveness of fab operations.

Mike Hilton, Senior Vice President & General Manager, Electronics & Performance Materials, Air Products

Going into 2008, the global electronics industry's outlook was uncertain as the credit crisis, rising fuel prices and a weakening dollar all conspired to cloud expectations. Now that we have reached the halfway mark, the only thing that is clear is that uncertainty is still here.

Despite global economic issues, utilization rates for materials consumed in semiconductor manufacturing remain strong. In addition, the industry is experiencing supply constraints for a number of raw materials including silane. This can be attributed, at least partly, to strong growth in the display and photovoltaic (PV) markets.

The market for displays has been significantly growing at or above expectations, so far, in 2008, and PV, particularly thin-film PV, while still embryonic, has shown robust growth as well. In the PV manufacturers' quest for a sustainable alternative to fossil fuels, a number of producers have turned to thin-film PV, which are manufactured in much the same way as thin-film transistor liquid crystal displays (TFT-LCD) are produced. At this point, it seems that new projects are being bid and announced just about every other day.

One particularly challenging area in 2008 has been equipment, as the electronics industry has reduced capital spending. Although 2008 was expected to be off from recent strong growth numbers, it has shown to be slower than expected, and is projected to continue to be tough in the near term.

While navigating the real world challenges facing our business today, it is important not to neglect innovation and the advances necessary to support the next technology nodes. That can be in new materials or complementary offerings that provide customers a head-start on integration, a reduction in development time and lower costs.

Paul Blackborow, CEO, Energetiq Technology

As you walk around the show this year, expect to hear more talk about extreme ultraviolet lithography (EUVL). Great strides are being made on the EUVL front, as EUV is firming up its position as the next-generation lithography technique of choice for 32 or 22 nm nodes, with memory manufacturers leading the way. There was much encouraging news over the past year for EUV viability from ASML, with the shipment and operation of the first two EUV alpha demo tools at Albany and IMEC. AMD and its development partners have demonstrated the first working chips using EUVL on the ASML EUV tool.

Although EUVL has had a long development period, it is starting to reach its potential with the essential infrastructure beginning to take shape. Mask defects are being reduced and are on track to meet the level needed for high-volume manufacturing. High-power lightsources have also made good progress. In addition, we have seen greater levels of investment by the infrastructure companies in the low-power lightsources needed for optics testing, resist testing, mask inspection, etc. Sources have been shown to be stable and repeatable for these metrology applications. Stepper manufacturers are beginning to move from concept tools to planning for high-volume machines, and orders are starting to be placed.

Immersion technology, combined with double exposure and double patterning techniques, is being stretched pretty far at the 32 nm node, and the consensus in the industry is that the most viable technology choice for next-generation lithography will be EUV. The next year promises to bring continued growth to the development and adoption of EUVL as it advances to becoming the preferred method for high-volume manufacturing.

Bill Ramus, Senior Vice President, Commercial Management, ILS Technology

Nearly a decade ago, Sematech began working with equipment suppliers and software companies to develop industry guidelines for giving equipment suppliers external access to fabs, with the objective of reducing equipment's cost of ownership (CoO). Improvements in CoO were to be accomplished by increasing equipment availability by reducing the average time needed for repairs and reducing out-of-pocket maintenance costs through collaborative, real-time knowledge sharing during the diagnosis and repair of fault incidents. This “e-diagnostic” initiative was the first of many projected nodes on the e-manufacturing continuum. There are now many emerging use cases of secure, collaborative remote access in our industry.

The cornerstone of the original initiative, and these now emerging use cases, was, and still is, security. Security in this context has two components, the first being the protection of network topology for all parties (e.g., protection from viruses and hackers, the ability to control sources and destinations, etc.). The second has to do with protecting all parties' IP by controlling user access to specific information sources and assigning specific use capabilities to individual users.

The widespread adoption of e-diagnostics has demonstrated to the industry that remote access is secure. Providers of managed remote services have gained the industry's confidence and trust. Fabs, fabless chipmakers, mask manufacturers, OEMs and parts suppliers are now all using remote-access services to optimize their operations' efficiency. Current uses, or those projected in the near-term, include predictive and preventive maintenance; chip design for manufacturability; equipment pre-qualification by fabs to OEMs; collaborative equipment matching between OEMs and fabs; sharing manufacturing execution systems and/or advanced process control information between OEMs and fabs; supply chain management; and OEM monitoring of outsourced manufacturing.

Considering our industry's increasing focus on efficiency and the prevalence of partnerships and alliances, it's no wonder that the managed service of remote access is becoming a first principle in communication between fabs, their suppliers and partners.

Nigel Hunton, President & CEO, Edwards

Current economic conditions and environmental impact have become increasingly critical factors in capital equipment purchase decisions over the past year. These worldwide concerns are likely to be a focal point at this year's SEMICON West.

Rising global consumption of oil and fears about supplies have forced crude oil prices to surge to new records of over $120 per barrel in recent months. This, among other things, has driven demand for more cost-effective and energy-efficient process equipment in the fab.

As much as 20% of a typical fab's overall energy consumption can be attributed to process vacuum alone. Even small efficiency improvements in this area can have a significant positive impact on costs while also reducing process carbon footprint, an issue that will be of increasing economic and regulatory concern in the future.

I am pleased to see that this year's SEMICON West show is being held in conjunction with Intersolar North America, a leading solar energy show. Not only is solar energy likely to play a significant role as a source of renewable energy, but the manufacturing process for solar cells shares much of the same technology used to manufacture ICs, including requirements for clean, efficient vacuum and abatement solutions.

Martin Van den Brink, Executive Vice President, Marketing & Technology, ASML Holding NV

This year's SEMICON West show will, as usual, be largely focused on solving the increasing challenges of producing transistors at ever-smaller dimensions. An important new trend is emerging, however, as the semiconductor industry begins shifting away from considering IC design, mask creation, lithography, metrology and other aspects of chipmaking in isolation. To produce today's leading-edge devices, a much higher level of coordination is required.

Improved lithography systems will, of course, play a big part in advancing the industry's technology capabilities. But a more holistic approach that considers the entire chipmaking process from start to finish will be essential to boost productivity and yields while paving the way for even smaller, more powerful devices.

Already, ultralow k1 lithography techniques, such as double patterning, are allowing the industry to produce devices at the 32 nm node. Yet, as manufacturers begin to implement these new design rules, the unique characteristics of the entire design and manufacturing process must be taken into account. Masks and illumination sources need to be co-optimized, for instance, while in the case of double patterning, designs must be adjusted to make them easier to split between multiple masks and to make sure that the manufacturing tolerances are respected.

Holistic lithography manufacturing increasingly relies on computational lithography. Besides optical proximity correction (OPC) and verification, computational lithography will soon be widely used to optimize parameters, such as overlay, critical dimension uniformity and application-specific scanner tuning. More and better metrology data also will be needed to fine-tune the lithography process.

Richard A. Gottscho, Group Vice President & General Manager, Etch Businesses, Lam Research Corp.

Economic uncertainty has exacerbated cost-sensitivity across the industry. As semiconductor manufacturers continue pursuing their technology roadmaps to remain competitive, this uncertainty has refocused attention on implementing strategies that lower the cost of ownership of toolsets and manufacturing. Extending the capabilities of existing tools to another process generation is an effective means of accomplishing this goal. As a result, at SEMICON West 2008, we expect to see renewed emphasis among equipment suppliers on extending proven technologies rather than introducing revolutionary new technologies. Double patterning and 3-D integration are two examples of the types of scaling approaches likely to be featured at this year's show.

As technical and economic hurdles continue to delay the introduction of extreme ultraviolet (EUV) lithography, double patterning techniques are becoming key enablers for the industry transition to 3X nm manufacturing. The challenge for etch system suppliers will be extending the capabilities of the installed tool base for double patterning.

Technology extendibility will play a key role as well in ramping solutions for emerging 3-D structures — where development is driven by both cost-sensitivity and the miniaturization trend in mobile electronics. Plasma etch technology, used extensively for deep silicon etching in memory and MEMS device production, is well suited for creating the through-silicon vias (TSVs) for 3-D ICs. Critical factors for the etch process will be the ability to etch a variety of materials within the same chamber while maintaining repeatable profile control.

Independent of process technology, the focus of exhibitors at SEMICON West will be on cost-effective scaling of existing solutions, such as upgrades that extend the life of installed equipment. Companies pursuing this approach are likely to be the big winners in the next year.

Geoff Irvine, Director, Commercial Development & Marketing, SAFC Hitech

From our point of view, there are a couple of areas of interest at this year's SEMICON West. At last year's show, the industry was entering an “age of chemistry.” A year down the line, the “age of chemistry” is without doubt upon us, and materials technology is playing an increasingly important role in the evolution of the semiconductor market.

The demand for new precursors continues to accelerate in a pressurized environment, where shorter times to high-volume manufacturing (HVM) are critical to gain competitive advantage in spite of increasingly exotic chemistries and materials employed. With many of the major chip manufacturers ramping up to HVM in high-k materials, we are already looking well beyond that, anticipating the challenges of the subsequent generations of chemicals that will, in time, replace the current materials of choice. It will be interesting to see what the focus of OEMs and IDMs will be at the show, and who else is looking beyond the next corner in the road.

Increased collaboration between chemical suppliers, OEMs and IDMs to address the challenges of the chemistries required to manufacture advanced materials to the high purity levels and in the volumes required, allied to developments in the delivery systems to transport these materials to the surface of the wafer to ensure optimal chamber performance, remain key success factors in the continuation along the materials roadmap. Ensuring that materials development and delivery to the market is executed in an economically viable manner means that cost of ownership models become increasingly important, especially in light of the newer materials being employed or currently under consideration. With a number of the materials being looked at from a device physics standpoint, being rare or precious metals, it will be interesting to see how this plays out, and if we experience cost vs. performance trade-off, as some materials could become premium commodities.

Bruce Hueners, President & CEO, Palomar Technologies

2008will see a continued focus on emerging packaging technologies and development of the equipment, process methods and know-how to interconnect these devices. Capabilities include unique wire looping for high-frequency devices; custom, low-profile, fine-pitch interconnects via gold ball bumping; and high-heat transfer eutectic die attach for high-power LEDs and VCSELs.

The holy grail of die and wire bonding — adaptive, closed-loop process control in critical microelectronic assembly processes — is nearing reality. Data acquisition tools, coupled with near real-time computing, can monitor and adaptively control the wire bonding process in some of the most advanced bonders. For applications that require high thermal dissipation, high reliability, high frequency, precision and ultraclean processes, a gold bump provides an alternative to Pb-Sn solder joints. As applications operate at speeds to 50 Gb/sec, limitations of the wire interconnect will force a redesign to incorporate a gold bump and flip-chip connection.

An equally important trend is the increased caution within U.S. companies to remotely outsource, due principally to four factors:

• Preservation of intellectual property in a global economy where everything is driven to a commodity.
• A focus on specialization to build competitive barriers in a market niche.
• Assimilation of complex, volatile information with the ability to swiftly execute.
• Risk mitigation and the potential cost of failure (i.e., get it right the first time or you miss the market window).

It is now clearer that there are significant risks to businesses that follow the outsourcing trend to its logical conclusion, namely dilution of brand equity and the ability to competitively differentiate irreversible loss of critical IP and overreliance on a remote geographic supply chain with freight costs spiraling upward. This has spurred the emergence of a class of “near-sourcing” alternatives, regional CEMs that are a lower risk alternative in many cases. These regional CEMs will be increasingly evident.

Paul Totten, Director, Semiconductor Marketing Swagelok Co.

The complexity of moving to new ground in the semiconductor industry — scaling, new materials and chemistries, and even new processing techniques — is increasing exponentially, and so is the required number of discrete solutions. Development costs are rising formidably, as is the risk associated with technology investment decisions.

One result is that component providers and integrators are assuming more of the risks and costs of new development and providing solutions that are unique to the project at hand. The standard product with the standard set of catalog variations still exists. But, alongside it — and just as important — is the product that is always changing and being reengineered for a new tool, new process or R&D.

Developers are reengineering products to meet new temperature tolerances and tighter temperature variances, improved status reporting and data logging, or are consolidating several functions into one component. In short, discrete, passive components are no longer adequate to support certain developmental needs of semiconductor manufacturers.

Today, suppliers to the semiconductor manufacturing market must listen, intimately understand the customer's challenge, ask the right questions, and provide a solution that has measurable impact on the process. This growing interdependency between supply chain and technology development is critical to the mutual success of companies in the semiconductor market, particularly at a time when the demand for technological advancement must be carefully and thoughtfully balanced with the cost sensitivity of the marketplace.

Further, as existing fabs try to improve their operational efficiencies and competitive performance by deploying a repurposing strategy, total cost of ownership once again becomes a prevailing consideration for future success. So today's suppliers are also being challenged to innovate around issues like chemical consumption, predictive maintenance, waste reduction and environmental controls.

Amidst all of these challenges, there is good news for the industry. Our market enjoys a healthy reputation for its innovative thinking and collaborative relationships, and the future belongs to those who can provide timely solutions that meet the new demands of the industry.

Jeroen Bloemhard, Global Executive Director, Electronics & Advanced Technologies Industry, Dow Corning Corp.

With the delay in implementing extreme ultraviolet (EUV) lithography, advanced 193 nm lithography technologies, such as immersion lithography and double patterning, are projected to extend optical lithography processes to the 45 and 32 nm half-pitch technology nodes. However, as half-pitch feature sizes scale to 45 nm and beyond, semiconductor device manufactures need new thin imaging layers to achieve high resolution, wide process windows and competitive cost of ownership.

Spin-on silicon-based photoresists or antireflective coatings (ARCs) with increased etch selectivity emerge as solutions for thin imaging layers, whether used in bilayer resist or multilayer resist lithography process schemes, respectively. Photoresists or ARCs formulated with silicon resins are deposited using a spin-coat track process without the need to transfer to a chemical vapor deposition (CVD) chamber. With companies working together and focusing on what each company does best, the development cycle for products using silicon resin is shortened. Ultimately, this helps to get much-needed silicon-based photoresists and ARCs to market faster.

Franklin Kalk, CTO, Toppan Photomasks Inc.

Collaboration and consolidation have become embedded in our industry vernacular. Collaboration refers to companies banding together to reduce R&D costs and time to market. Consolidation portrays manufacturing capacity as increasingly becoming the domain of foundries or joint ventures of erstwhile competitors in the name of production cost, capital leverage and cycle time. Both models continue to evolve as the industry meets demand for consumer products with stringent cost and cycle time requirements.

Collaboration is now spreading across the supply chain under the guises of design for manufacturing (DFM) and design for test (DFT). High design and back-end costs are prompting like-minded companies to share costs and expertise. For example, lithography collaborations now routinely include optical proximity correction (OPC), mask, scanner, track, wafer and resist suppliers.

The relative importance of manufacturing and IP are different for memory, microprocessor, logic and analog business segments. In logic, for example, manufacturing can be outsourced to foundries because differentiation is a function of IP, efficient product design and timely, low-cost manufacturing. The next wave of logic industry consolidation is now visible as companies begin to outsource tape-out operations and depend on wafer foundries for standard IP.

Conversely, manufacturing technology and scale rule the memory sector. Unable to depend on product design as a differentiator, memory companies must run their own fabs. The recent fall of memory prices and continued escalation of leading-edge manufacturing capacity investments will force more consolidation; those companies with high manufacturing costs risk failure.

As semiconductor business models continue to evolve, one thing is certain: Collaboration and consolidation will be dominant themes, and their primary drivers will be cost and cycle time.

Steven Dwyer, Vice President & General Manager, North America, EV Group

Through-silicon vias (TSVs) and 3-D integration will again be a key theme this year at SEMICON West. Consumer demand for more portable handheld devices continues to drive production of memory devices and CMOS image sensors, which, along with MEMS, are the primary applications driving the adoption of TSV and 3-D integration technology. We are seeing a lot of movement in this area — where there have been several false starts over the past seven years, the work now being done in this area is very real, the technology is being implemented, and revenue and order intake are now being realized.

Another reason commercialization of TSV technology will be a major topic of discussion at SEMICON West is their potential for helping drive down interconnect/packaging costs by enabling the creation of shorter, smaller-diameter vias with lower aspect ratios. Although performance and quality are closely linked, cost reduction continues to be a primary decision factor in the equipment space — most customers won't consider implementing any new process or technology unless it directly impacts cost, whether per wafer, per die or per transistor.

Techniques for handling thin wafers, especially for those with thicknesses down to 35 µm, are the catalyst for another key theme at SEMICON West: wafer-to-wafer bonding. Temporary bonding technologies facilitate thin-wafer processing with standard fab equipment, as well as enabling standardized handling solutions for every tool without necessitating special chucks, cassettes, etc. This is an area in which the industry has been diligently working.

Tom Caulfield, Executive Vice President, Sales, Marketing & Customer Service, Novellus Systems

As the growth of the semiconductor industry becomes increasingly fueled by consumer applications, the trade-off between balancing technology needs and profitability becomes critically important. IC manufacturing processes for the next technology nodes are becoming more complex, specialized and, in most cases, more costly. To meet this challenge, semiconductor manufacturers are seeking equipment that can deliver advanced technology and high productivity while reducing overall operating costs.

We already see evidence of this trend in high-volume production environments, such as the memory “megafabs” that require specialized systems capable of extremely high throughput. For example, dielectric plasma-enhanced chemical vapor deposition (PECVD) tools that process up to 250 wph — a capital productivity increase of more than 25% when compared with traditional offerings — are becoming the tools of choice.

At SEMICON West 2008, we will see a variety of cutting-edge technologies promising productivity gains and capital extendibility in a multitude of applications, including dielectric gap fill. At 45 nm and below, ensuring high-quality, void-free dielectric films for gap-fill applications is critical, but so is reducing the cost per wafer. As a result, high-density plasma (HDP) CVD technologies geared toward high-aspect-ratio device structures will focus on process reliability, extendibility and delivering the lowest cost of ownership.

Continued device scaling by the semiconductor industry has led to a need for more robust patterning schemes using ashable hard masks, as well as a necessity for highly doped shallow transistor junctions. These trends add to the complexity of photoresist ashing during IC manufacturing, and are partly responsible for creating a divergence between applications for advanced logic and memory. At SEMICON West, we will see the emergence of dry strip and clean technologies that offer superior productivity gains while also meeting the technical challenges of low silicon loss for shallow transistor junctions, as well as the ultralow defectivity required for advanced technology nodes.

Erik Smith, President & COO, Qcept Technologies

With the semiconductor industry in the midst of a downturn, leading IC manufacturers are shifting emphasis from capacity expansion to new chip designs — as well as new materials and processes — to produce the next generation of devices that will open up new consumer applications and market opportunities. Many of the product introductions and technology announcements at SEMICON West will support these efforts.

With any new technology introduction comes the risk of yield loss associated with process and material integration. In this increasingly competitive manufacturing environment, every day saved in yield learning during the development phase, and every percentage of yield improvement in production, can make the difference in first-to-market status and profitability. Yet, implementing more of the same yield management methodologies is not the answer, as these new materials and processes produce a growing number of yield-loss sources that are undetectable with optical inspection solutions. In leading fabs, these “non-visual defects” (NVDs) make up as much as 30% of fab losses. With the number of process steps and the complexity of new materials integration on the rise, the impact of these NVDs will only become greater if no solution is found.

Luckily, new innovations in NVD inspection can address these growing yield challenges cost-effectively and without impacting manufacturing productivity. Advanced fabs are beginning to obtain benefit by incorporating NVD inspection into their yield management and process development toolset, and I expect this trend to continue.

Adrian Kiermasz, President & CEO, Metryx

While the economic forecast for the semiconductor equipment industry is somewhat unclear for the rest of this year, there are a number of positive reports that the inventory of semiconductor devices is not massive and capacity utilization is at 90%. Hence, it appears that plans for capital expenditure remain conservative during 2008 in anticipation of steady or increased demand for devices.

Whatever the eventual market forecast outcome for 2008, being a part of the semiconductor industry has never been more interesting. Technologically, there are two directions being explored. First is extending Moore's Law and utilizing the CMOS transistor and supporting peripheries with new materials and processes to the furthest node possible. Second, new devices (such as MuGFETs) are being fabricated and developed, again, coupled with new materials, process technologies and fabrication techniques.

New developments that involve new materials and processes offer various degrees of risk and, in the conservative semiconductor manufacturing arena, risk is to be mitigated at all costs. To provide a cost-effective solution to risk mitigation, new metrology methodologies are being developed that add positive value to the device flow. There are many different types of metrology. Fundamentally, however, all metrology performs the same function: It provides information on a given process for the end user to make an informed decision on what to do next. To have this capability, metrology products must attain high product wafer sampling rates, high resolutions, immediate feedback, high throughputs and be cost-effective -- that is to say, they must make a real difference and have a positive impact to production lines. Interest has never been higher for metrology that can achieve this, as it enables device manufacturers to implement new processes with minimum risk and obtain higher productivity and faster time to market.

Bob Tucker, Vice President & GM, Entrepix

While there will always be a focus at SEMICON West on new products and tools for leading-edge technology node manufacturing, over the past few years a significant market has developed focused on extending the life of 200 mm equipment and facilities. We've seen “200 mm prime” really come to the fore, with it included in the ITRS under the moniker “More than Moore.” 200 mm prime fuels next-generation 200 mm processing by improving productivity, longevity, cost and technology.

200 mm prime enables device manufacturers, in tandem with equipment suppliers and a vast network of third-party outsourced service providers, to increase productivity in two primary ways: through improvements to materials, processes or the tools themselves that make 200 mm manufacturing more cost competitive with 300 mm fabs, or through the introduction of new technologies on old toolsets, such as analog, power, MEMS, nanotechnology or photovoltaic manufacturing, to name a few.

So how can 200 mm prime be successful when a significant number of toolsets are no longer supported by the OEMs? The answer lies primarily in OEM Eco-partner (sometimes known as “OEM Authorized”) agreements that allow outsource providers who have an intimate understanding of the tools and processes to provide service, upgrade packages and process development on the OEMs' behalf. This win-win allows chipmakers to breathe new life into, and earn profits from, their fully depreciated assets.

The third-party outsourced providers qualified as “OEM Authorized” provide a critical resource for solving the limitations of existing 200 mm toolsets. Their core competency is to bring service expertise for legacy tools, along with process and materials expertise, to develop unique solutions for older facilities whose days are anything but numbered.

Philip Garrou, IEEE Fellow & Consultant, Microelectronic Consultants of NC

The theme I suggest you look out for at this year's SEMICON West is the convergence of IC and discrete manufacturing with post back end of line (BEOL) packaging.

It was over a decade ago that Unitive (now Amkor) and Flip Chip Technologies (now Flip Chip International) introduced and licensed their wafer-level packaging (WLP) technologies to the world. These wafer-based packaging processes continue to gobble up market share, and it looks as though foundries are now looking hard at entering the market.

Just when we thought discrete passives could not get any smaller, passive integration comes along. IDMs, such as STMicro (IPADs) and NXP (PICS), have moved programs into high-volume manufacturing, and a number of OSATS are also ramping up to do so. If you're looking for a way to continue to shrink portable consume products and haven't heard of passive integration, ask about it at SEMICON.

Is this the beginning of the end for CMOS? Is production ramping for 3-D IC integration?

What started in 2001 as a warning from professors at Stanford, MIT and Georgia Tech was echoed in 2007 by senior technologists at IBM and Toshiba and openly discussed by the Energy Information Administration. CMOS device shrinking, as we know it, will come to an end somewhere in the 32-22 nm node, depending on the device. Key 3-D technologies are using “through-silicon vias” (TSVs), wafers thinned down to 10-20 µm and even thinner for silicon on insulator wafers and bonded, most likely using metal-metal bonding. Four major players in the CMOS image sensor market have already announced capacity for TSV-based modules; memory stacking has been shown to be technically (if not economically) viable by Samsung, Elpida and Micron; and 3-D integration technology has been shown by Intel to alleviate the severe latency problems expected for multicore processors. You will now find 3-D on the roadmaps of many IDMs and OSATS, including Amkor, ASE and STATS ChipPAC, to name a few. Recent announcements by TSMC make it, I think, a slam dunk to move forward in a big way.

Mark Melliar-Smith, CEO, Molecular Imprints Inc.

The future of optical lithography — an ever-more critical issue in the semiconductor industry — will most certainly be one of the leading topics of concern at SEMICON West this year. Indeed, one of this year's themes is “Semiconductors in Transition: Exploring the Innovations in Materials, Machines and Manufacturing That are Moving the Microelectronics Industry to the Limits of Moore's Law and Beyond.” It's no wonder, as photolithography's continued extension has become increasingly difficult and expensive, that Moore's Law is in jeopardy. The use of high-NA immersion exposure tools has driven lithography tool cost to more than $40M. Double patterning increases the number of tools, materials consumption and process complexity, adding cost, time and yield issues. Device designers must also contend with very restrictive design rules, aggressive optical proximity correction (OPC), complex and costly phase-shift masks, and extensive computer horsepower to support the modeling requirements associated with computational lithography. Yet, even with all of this added expense, the extendibility of 193 nm lithography is limited and a better technology is required.

The industry has invested hundreds of millions of dollars and many years in extreme ultraviolet (EUV) as one possible replacement, but doubts continue to build around its economic and technical viability. Very complex mirrors must replace lenses, the tool must be located in high vacuum, 13 nm X-ray sources are built from very high-power plasmas, and the resist material must be a factor of 10 “or greater” more sensitive than standard UV resist. Estimated costs for EUV systems are approaching $100M, and the date of availability continues to be pushed out as technical challenges prove too daunting to overcome.

As a result, the semiconductor industry is giving serious consideration to another alternative technology — nanoimprint lithography. Leading-edge non-volatile memory manufacturers dealing with tight cost constraints and shrinking resolutions have begun validating step-and-flash imprint lithography (S-FIL). This nanopatterning technology, which has always brought excellent resolution, line-edge roughness/linewidth roughness, and low cost of ownership, is overcoming the overlay and other technical challenges that previously were roadblocks to nanoimprint. It uses the existing optical lithography infrastructure, including commercially available photomasks, resists and sources, and is a drop-in complement to 193 nm lithography in a mix-and-match environment. As a result, S-FIL has become a leading candidate to keep the semiconductor industry on track with Moore's Law — without the cost, complexity or disruptions in process flow associated with double patterning and EUV.