Industry News: Haze Concerns, Nanophotovoltaics, Physical Chip Analysis
Staff -- Semiconductor International, 6/1/2008
Haze, Still Misunderstood, Costs Industry $1B/Year
Arguably the single largest yield detractor in the semiconductor industry, costing the industry about a billion dollars every year, micro-contamination is still very little understood or acknowledged by semiconductor fabs. "Even though the semiconductor industry is a mature industry, it's really in its infancy in understanding micro-contamination," noted Brian J. Grenon of Grenon Consulting Inc. (Colchester, Vt.). Haze, visible or printable crystalline structures that grow from contamination on masks, has been a significant issue for the semiconductor industry for more than 10 years, and yet semiconductor manufacturers are still not on board with coming up with solutions, according to Grenon.
Grenon made these comments at ESTECH 2008, the Institute of Envinromental Sciences and Technology's (IEST) multi-industry contamination-focused conference in Bloomingdale, Ill. Speaking in a session devoted to the topic of time-dependent haze, Grenon noted that fabs still see haze as a problem that their suppliers need to take care of.
The problem, specifically, is that haze is forming on wafers, photomasks and optical elements, degrading surfaces, causing increased downtime for cleaning, or even catastrophic failure. Some of the micro-contaminants are being deposited by cleaning processes, and many are deposited from the environment. Still others are introduced by the packaging used to transport the elements. Photomasks are more susceptible to haze than are the optics within a lithography scanner, according to Oleg Kishkovich of Entegris (Chaska, Minn.), largely due to construction materials, environment and purge dynamics.
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| Optical and SEM images show ammonium carbonate haze formation. (Source: Grenon Consulting) |
Dominion Semiconductor was the first to report yield loss from ammonium sulfate haze around 1997, when the company lost some $25M in one day. Since then, essentially every semiconductor fab has experienced some form of haze contamination, according to Grenon, who showed a global map of haze contamination. In some cases, the loss actually outstripped revenue, with the largest loss reported to date being $100M. The worst effects have been seen in Taiwan and Shanghai, China, where environmental factors figure prominently, he said. And the problem is not getting any better. The higher energy of the shorter-wavelength lasers being used in lithography, as well as larger wafer sizes, are aggravating the issue. The most recent major incident was only about three months ago in Korea.
The issues have been difficult to quantify because nobody wants to admit that they actually have a haze problem. In the photomask industry, where extreme competition makes maskmakers hold every bit of information close to their chests, it is difficult to get data, for example, on how many times masks are cleaned. But in fact, the surfactants that maskmakers use to clean the photomasks are a significant cause of haze, and Grenon contends that he can tell how many times a mask has been cleaned by how many layers of contamination are built up on it. "We find that the more you clean, the dirtier it gets," he said.
Surfactants have been identified as a key ingredient to avoid in cleaning processes because of the haze they leave behind. "The worst possible clean you can do with an optical element is put it in a surfactant," Grenon said.
Wafer supplier MEMC Electronic Materials Inc. (St. Peters, Mo.) stopped using surfactants to clean the packages used to transport its wafers, and found that they were able to keep haze much more under control, according to Larry Shive, MEMC Science Fellow. Because haze continues to grow over time, it can greatly reduce the storage shelf life of a wafer, for example. But with changes it has made to its processes, MEMC has been able to extend the storage time for its wafers from six months to 18 months.
As Shrive explained, time-dependent haze (TDH), also known as degradation haze, is formed in the following way:
- The wafer is contaminated with water-soluble ions and organic molecules (other organic molecules also deposit on the wafer, making it more hydrophobic).
- A change in humidity causes water to condense on the wafer surface.
- The surface water dissolves the water-soluble contaminants.
- The hydrophobic surface causes the water to form microscopic droplets.
- The micro-droplets evaporate and leave residual TDH defects.
Without humidity, micro-contamination does not develop into haze. So one thing MEMC did was to implement measures to get the moisture out of its manufacturing facilities (air is kept at 27% RH) and reduce the amount of moisture that gets into the package. Although keeping humidity low in the facility was easy enough because wafer manufacturers do not have to worry about electrostatic discharge as much as device manufacturers do, the second factor was more difficult, Shrive said, because they are cleaning thousands of packages a day.
Besides doing away with its use of surfactants, the company focused on moisture barriers for its packages (including adding desiccants to the package) and maintaining the package integrity. MEMC has found instances, for example, in which the aluminum packaging has been torn by the metal shelves where they are placed for storage. With even the slightest pinhole in a package, moisture can enter, causing haze formation. In the past, the best way to find a pinhole in a package was to put the package over your head and see if any light came through — "not very elegant." Instead, MEMC has developed oxide thickness determination method that measures the oxidation inside the package.
MEMC also found that some packages they were using released unacceptable amounts of organic carbon, which almost guaranteed degradation, Shrive said, so they stopped using those packages. Sulfate is a known problem with degradation haze, so they have also been careful not to have any sulfate present in the environment.
Ammonium sulfate, which caused the first reported haze, has become widely known as a micro-contaminant, so is largely under control because the industry has removed sulfate from the environment. But that doesn't mean haze has been solved — only that the industry has since encountered new contaminants. Despite all of the changes, the organics are still there. "All you're going to do is change the molecules that get adsorbed on the surface," Grenon said. The latest haze, he noted, is ammonium oxalate, which is created by carbon dioxide and water in the air, along with ammonium (which will always find its way into a facility, according to Mark Camenzind, Air Liquide — Balazs Analytical Service).
While haze can mean millions of lost dollars for a single fab, maskmakers are happy to take the reticles back for cleaning because it means more income for them. And because of haze, fabs are now ordering three masks where they used to order two: After the first one develops haze, it goes back to the mask shop to get cleaned and re-pelliclized, the second mask goes into production, and the third is there for the backup that the second used to be able to provide.
—Aaron Hand, Executive Editor, Electronic Media
Harvard Creates Nanophotovoltaic With Macro Potential
A Harvard University (Cambridge, Mass.) research group headed by professor Charles Lieber has developed a ~300 nm-thick coaxial silicon nanowire that could form the basis for a photovoltaic (PV) cell used to power small circuits and nanomachines.
The experimental silicon cell has demonstrated an efficiency of 3.5%, which is considered adequate for an experimental device of this kind. High-current densities have been attained on the order of 24 or more mA/cm2, which is better than what can be done in organics or most hybrids. The power is up to ~200 pW, although occasionally 1 nW has been observed, and the group's early work indicates that the voltage or current could be doubled by hooking two nanophotovoltaic devices in series or parallel.
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| The nanophotovoltaic has a coaxial configuration made up of three differently doped silicon regions, which enable it to function as a regular solar cell. Seen here is the positive core, already etched and ready for the first contact. (Source: Harvard University) |
"We considered many schemes, including several nanostructured materials," Lieber said. "We began by exploring how to improve charge collection by changing the traditional planar configuration photocell geometry and settled on a coaxial geometry." Because the layers are radially aligned, a coaxial format shortens the collection lengths, providing higher efficiency. In the circular cross-section, electrons and holes must move across considerably shorter distances. Also, it becomes possible to use lower-quality materials without suffering losses. Overall, the process lends itself to making PVs on plastics or almost anything else.
Fabrication begins with the growth of a p silicon nanowire core, a single-crystal structure grown by using a metal nanocluster that nucleates the growth via vapor/liquid/solid growth. The diameter is controlled by the size of the metal catalyst particle used to nucleate. Once the core is done, nanowires are sequentially deposited, forming an intrinsic layer of various thicknesses and then creating an n shell to cap it, resulting in the basic p-i-n core/shell/shell structure. The device can be optimized by varying the thicknesses and doping of the layers.
The nanowires are randomly grown on a substrate that can be something as simple as glass. Then a piece of the substrate is put into ethanol and sonicated for five seconds to shake the wires suspended in a solution. The wires are dropped onto the chip where the devices will be built.
Electron-beam (e-beam) lithography is used to fabricate contacts to the n shell and p core. A mask and wet etch are used to expose the p core, creating what appears like a stinger-like end coming out of a thicker diameter core. This fine rod is what is left after one of the nanowire's ends has been etched, and single or multiple contacts can be made to it afterward to determine whether efficient radial collection is obtained. Only two contacts, one on each end, are necessary to complete the device. It is also possible to just etch the end of many of these nanowire elements and put a single p contact to the core to link any number of them and produce an array of parallel devices.
"This is a very robust, completely inorganic system, and like other inorganic PVs, very stable," Lieber said. "We have operated devices for about a year without any degradation, as well as at a 10-sun illumination with very stable behavior. Organics or polymers don't tolerate concentrated sunlight well." With proper packaging, these nanophotovoltaic cells could last decades, he added.
At present, this proof-of-concept effort has produced devices capable of powering a biosensor or small logic gate. The main focus now is to raise device efficiency to 10% and beyond.
While there is no expectation that this work will solve large-scale power-generation problems, it is aimed at nanosystems that need power to function. Assembling them with nanophotovoltaics could offer a way to fabricate integrated, self-powered nanoscale devices.
—Alexander E. Braun, Senior Editor
Physical Analysis Provides Images of 45 nm
From the different ways that strain is being implemented to the complexities of high-k/metal gate, the engineers at Chipworks Inc. (Ottawa, Canada) have uncovered many physical details of the 65 and 45 nm process technologies. Dick James, senior technology analyst for Chipworks, provided an overview of the firm's latest analyses at the Advanced Semiconductor Manufacturing Conference (ASMC) in Cambridge, Mass., May 5–7. Among these were two 45 nm chips: the Intel Xeon and the UniPhier parts from Matsushita Electric Industrial Co. Ltd. (Osaka, Japan).
For simplicity, Intel (Santa Clara, Calif.) forms the NMOS and PMOS transistors in a common trench. The PMOS uses embedded SiGe (eSiGe) with 25–30% graded germanium concentration. The contacted gate pitch is 160 nm with a gate length of ~42 nm and NiSiGe contact silicide spaced from the channel. The 1.5–2.0 HfO/ZrO dielectric has an underlying SiO2 interface of ~1.1 nm. The metal gate is a TiN/TiAl/Ta/TiN stack (Figure). The NMOS transistors feature 42 nm metal gates and a TiAl gate. The silicide is NiSi with no platinum, possibly used to induce strain in the channel, according to James. The process flow involves depositing the high-k, TiN (for workfunction adjustment) and polysilicon. The dummy transistors are formed, including source/drains, silicide and contact etch-stop layer (CESL). The poly (but not high-k) is then removed, common tantalum and thick TiN are deposited, tantalum is etched from NMOS and filled with TiAl. The p and n workfunctions are controlled using a thermal treatment to form TiAlN in the NMOS gate.
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| Intel Xeon PMOS transistor features embedded SiGe (25-30% Ge) and a replacement high-k/metal gate. (Source: Chipworks) |
The Matsushita UniPhier 45 nm system-on-a-chip (SoC) device featured ~30 nm gate length, 190 nm contacted gate pitch, ~1.7 nm gate dielectric, NiSi and stress-enhanced transistors including a thin (10–15 nm) nitride CESL. "We are quite convinced that manufacturers are getting strain using very thin nitride layers," James said. He said the device is a fairly direct shrink of the 65 nm device.
In looking across the gamut of 65 nm and the two 45 nm parts, certain commonalities exist, including advanced strain and platinum-doped NiSi. Embedded SiGe is becoming increasingly common in PMOS, as are nitride tensile and compressive stress caps. Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) appears to be using <100> orientation for PMOS mobility enhancement, and at least one company is using stress memorization by implantation. James said that SRAM cell size has become a better indicator of scaling than gate length or M1 half-pitch, which is one of the reasons the International Technology Roadmap for Semiconductors (ITRS) is trying to get away from the designation of "node."
—Laura Peters, Editor-in-Chief
