Synopsys Unveils Faster Router

Laura Peters, Editor-in-Chief -- Semiconductor International, 5/27/2008 7:40:00 AM

Responding to the need to take better advantage of the multicore microprocessor architectures and solve 45 nm design for manufacturability (DFM) challenges in IC design, Synopsys Inc. (Mountain View, Calif.) introduced the Zroute compiler router. Using a combination of advanced routing algorithms and multi-threading technology, the new router has demonstrated a speed increase of more than 10× on customer designs.

Customer S3 Graphics (Fremont, Calif.) claimed that Zroute design converged 3.3× faster with single threading and achieved a 10× performance improvement using quad core machines.

In the area of DFM optimization, the router offers several advances, including accommodation of “soft” design rules, more efficient via doubling implementation and wire spreading/widening for improved performance. One example of improved DFM is more litho-friendly designs with fewer “jogs and notches.”

1. One customer claimed a 43% reduction in single-cut vias, 70% fewer narrow jogs and 30% fewer notches with the new router.

Synopsys estimates that more than 100 45 nm designs were being taped out or actively designed in 4Q07 (Fig. 2). The majority of this activity occurred on the predecessor to the Zroute, the Galaxy platform. Zroute is offered as a standard feature on IC Compiler, the company’s physical design platform.

2. 45 nm tape-out activity. (Source: Synopsys)