Electromigration-Induced Failures in Plastic Encapsulated IC Packages

A commercial CMOS digital potentiometer IC in an eight-pin small outline transistor package was demonstrating field failures after ~1 month of operation. Systematic failure analysis led to the identification of the failure mechanism: post-manufacture, metal migration inside the plastic-encapsulated package. Plated silver from the leadframe had dissolved and redeposited as metallic "stringers" along the interface boundary between the die attach epoxy and plastic encapsulate deep inside the package. The stringers created low-resistance electrical connections between adjacent leadframe legs that can carry hundreds of microamps of current (Fig. 1).

1. A SEM image of a silver migrated metal stringer, which caused a low-resistance connection between adjacent leadframe legs.

The potentiometer IC is one of many ICs assembled on the main PCB of a tabletop instrument that is continuously powered on in normal operation. The screen contrast on the instrument's LCD is set by the output voltage of the potentiometer. The output voltage (pin 1) is determined by an eight-bit digital value (the contrast setting), which is transmitted through an I2C bus (pins 4 and 5). In the context of this application, typical pin voltages range from 0 to 3.3 V (Fig. 2). The output voltage is a function of the contrast setting (Fig. 3).

2. Typical voltages on the pertinent IC in the circuit application.

There was no indication of digital potentiometer problems at chip-level or instrument-level production testing, and field returns caused by malfunction of this IC were latent. An increased rate of return occurred primarily after those instruments had been in use for ~700 hours (after they had been powered on continuously for one month). Instruments that had digital potentiometers from one particular IC assembly batch date code were observed to have a significantly higher return rate.

3. The pin 1 output voltage is a function of the contrast setting.

The typical symptom observed on faulty potentiometer ICs was a low-resistance path between the I2C clock line (pin 4) and ground (pin 3), but low-resistance paths between other pins were also encountered.

We determined that the failure mechanism was sensitive to temperature. Initially, low resistance between the I2C clock line and ground on the PCB implied a problem with the digital potentiometer, because the short would disappear when the digital potentiometer connection to that signal was broken (i.e., when pin 4 of the suspect IC was desoldered and lifted). However, when pin 4 was probed, no short-to-ground was observed, and when the pin 4 connection to the I2C clock line was resoldered, the instrument would function normally. Only when suspect digital potentiometer ICs were cut off the PCBs without the application of heat did curve tracing confirm a low-resistance path between pin 4 and pin 3 on isolated IC packages.

These pin 3/4 electrical shorts varied in resistance — from <100 to >800 Ω — and they often demonstrated an intermittent nature. For instance, excessive voltage or current would cause the low-resistance characteristic to be "lost," which is not surprising, but the "short" would return if the IC was exercised for several days in the typical application (Fig. 4).

4. Comparison of good (white) and shorted (red) pin 4 curve traces with respect to ground (pin 3).

Next, we isolated the fault location by milling through the IC package until the bond wires were broken (Figs. 5–7). By probing between the chip side and leadframe side of the broken bond wires, the electrical shorts were isolated to the leadframe side of the IC.

5. End-view diagram showing the orientation of die and leadframe, including the die attach epoxy.

In addition, because the substrate ties of ground pin 3 are the only designed electrical connection to the silicon substrate in this package (non-conductive die attach should insulate the substrate from the leadframe), curve tracing the broken bond wires could also be used to determine whether the low-resistance leakage path at pin 4 was between the leadframe leg and die substrate or directly between adjacent leadframe legs. The predominant leakage path occurred directly between adjacent leadframe legs and not through the die substrate. Of the 11 failures analyzed in-house, 10 demonstrated leadframe-to-leadframe shorting and one failed via a leadframe-to-substrate short.

6. The possible shorting paths are between the two leadframe legs and the leadframe and substrate. The pin 3 (ground) bond wire has substrate ties and should be the only electrical contact to the silicon substrate.

This conclusion was unexpected because only 10 μm (nominal) of die attach epoxy separates the leadframe from the die substrate, while adjacent leadframe legs are separated by ~150 μm.

7. Curve tracing showed that the pin 4 leakage current traveled directly between leadframe legs and not between the leadframe and die substrate.

We continued the milling process down through the die until the silicon substrate was entirely removed. This left a thin layer of die attach epoxy over the leadframe. It should be noted that the interface between the die attach epoxy and plastic encapsulate is saddle-shaped in the area between the leadframe legs. This is a result of the assembly process — the viscous die attach epoxy is first applied to the back of the wafer die, and the die are placed on top of the leadframe before the epoxy is fully cured. This process creates a fillet-shaped surface of epoxy between adjacent leadframe legs (Fig. 8). After wire bonding, the plastic packaging material is injected into the mold and the gaps are filled, creating saddle-shaped ribs of plastic encapsulate between the leadframe legs.

8. Side-view diagram showing the approximate shape taken by epoxy around the die and leadframe legs.

On the failing ICs, we observed metallic stringers under the thinned die attach epoxy in the region between the leadframe legs.

9. Stringer between leadframe legs.

10. Close-up of stringer (Fig. 9) under the thinned epoxy. The ends of the stringer are not visible because of the curved interface surface.

When the horizontal face-lapping plane was advanced into a stringer on a particular analysis sample, the silver metal was exposed at the interface between the epoxy and encapsulate (Figs. 11 and 12). The oval boundary between the die attach epoxy and plastic encapsulate (Fig. 12) is the result of the saddle-shaped interface intersecting with the horizontal face-lap plane. We used energy dispersive spectroscopy to identify the composition of the metal as silver.

11. Location of the epoxy/encapsulate interface.

Most documented cases of metallic electromigration (EM) or conductive anodic filament occur in the context of copper migration between layers of PCBs. However, a well-publicized case of IC failures related to silver

12. Darkfield microscope image of stringer from Figure 11 coming up to the epoxy/encapsulate interface. Energy dispersive spectroscopy was used to identify the metal as silver.

Investigation into the presented case of digital

13. SEM image showing migrated metal between adjacent leadframe legs.

The author is interested in hearing from peers who have encountered similar instances of failures caused by migrated metal inside encapsulated IC packages.

The author would like to thank several employees of Boston Scientific's Cardiac Rhythm Management unit, including Richard Thomas and Jeffrey Skaare for PCB analysis; Howard Bentley for IC failure analysis; Cory Klemmensen and Deanna Zeien, SEM imaging and EDS analysis; Bruce Peacock, materials analysis; John Kerrigan, quality assurance; and Donald Burr, supplier development.