Freescale Taking Redistributed Chip Packaging to Pilot Production Stage

David Lammers, News Editor -- Semiconductor International, 5/12/2008 9:32:00 AM

After six years of development, Freescale Semiconductor Inc. (Austin, Texas) is moving its pioneering redistributed chip packaging (RCP) technology to early commercial production, said Navjot Chhabra, RCP operations manager.

Wafers holding RCP-optimized chips aimed at MP3 players were received at Freescale’s Tempe, Ariz., facility earlier this month, to be followed in two months by Freescale-designed ICs for a Japan-based digital camera customer, Chhabra said. After several months of pilot-mode production in Tempe and product certification at the two initial customers, RCP will move to volume production in the first quarter of 2009 at Tempe, where Freescale has built a 12,000 ft² RCP production facility with a capacity of ~800,000 units per week. About 35 dedicated manufacturing people work at the Tempe facility, backed up by another 35 R&D engineers.

Freescale is moving its redistributed chip packaging (RCP) technology to pilot production in Tempe, Ariz. The approach attaches die to a 300 mm panel.

The approach has passed commercial-grade reliability specs. Over the next two years, Freescale’s plans call for RCP to be used to reduce the size and improve the performance of a wide variety of Freescale silicon, starting with wireless ICs and moving later to high-performance networking chips, digital signal processors (DSPs) and microprocessors.

“Our direction is moving from simply chip design and package assembly to system design and system assembly. We will be moving up the value chain,” Chhabra said.

Freescale has been developing the RCP technology since 2002, spurred by expectations that wireless RCP modules could shrink by 30% in the X, Y and Z dimensions. Because the RCP approach processes lots consisting of 25 300 mm panels at a time, there also are cost advantages, particularly over ball grid array (BGA) packaging, he said. Conventional BGA packaging uses expensive substrates and gold wires. RCP uses optical aligners and wet etch processes to define I/O connections with 25-30 µm feature sizes. The approach encapsulates and builds up the I/O connections using “low-tech, assembly-like manufacturing tools to keep the cost of RCP manufacturing low,” he said.

The RCP technology can shrink a wireless module in the X, Y and Z dimensions, and reduces noise and parasitic capacitances, according to Freescale.

Phased approach

At its simplest level, RCP replaces a BGA substrate. Freescale plans to move beyond that to a systems focus, combining heterogeneous components into a small substrate or platform. For some of Freescale’s 45 and 32 nm products, the I/O on the die itself will be optimized for RCP rather than brought out to the edge of the die for wire bonding.

With a systems focus, Freescale engineers can eliminate certain filters and other passive components, reducing noise and parasitic capacitance.

Phase I is to do single-die RCP assembly for external and internal customers, Chhabra said. Phase II, which he said is about a year away, is to use RCP to assemble a variety of components into a system module. Not all of those components need be RCP packages, he noted.

Stage III is to use die with the I/O optimized for RCP modules.

“The die today are designed for wire bonding, with the I/O all on the periphery. That takes a lot of area. RCP is like flip-chip, with the vias placed right in the center of the die. With RCP, we can design chips with a much smaller die size and get a huge benefit in terms of the front-end cost.”

The approach also supports a simpler board technology. Instead of using 10-layer boards, the RCP systems can use PCBs with three or four layers of routing with significant cost benefits.

“There have to be gross-margin benefits, and that means that our yields have to be as good or better than wire bonding, which has better than 98% yields,” he said.

The pilot production comes about 18 months after Freescale’s management made a December 2006 decision to build the pilot line. “We have made a commitment," Chhabra said. "Now we are ramping production, we have proven out the process, and there are five or six initial parts in Freescale’s wireless portfolio that are being looked at for RCP volume production. We have two chips that we are starting with in markets where we can win slots and sockets. Ultimately, we are in the business of trying to replace all BGA wire bond technology, but we know we can’t take it all on right away.”

Materials challenges

Chhabra said Freescale has overcome materials challenges, particularly the encapsulant and dielectric materials. “The concept is pretty simple; the challenge is in the materials. Getting the materials integrated together and passing reliability — people for years have struggled with those issues.”

The RCP approach starts by dicing wafers holding probed good die. The die have an interconnect layer defined by front-end processing for the RCP approach. Between 700 and 2000 singulated die are placed on a 300 mm panel using pick-and-place equipment. The encapsulant must hold the die motionless on the panel so the projection aligner can define the vias during the I/O build-up process. One challenge was finding an encapsulant that would keep the die from moving and that met Freescale’s filler, cure and temperature requirements.

Another was developing a dielectric that could withstand the stresses and strains without cracking. The RCP dielectric must be able to spin on in a planar form and be photo-imagible, with the right features for the 1500-µm-thick layers.

“There are a number of issues that come up with the dielectrics," Chhabra said. "You have got to be able to image it. The feature sizes are not what you see on the chip itself, but they must be photo-imagible, starting with 30 µm lines and spaces and going down step by step to 10 µm. We start out with 80 µm vias and plan to go down to 40 µm vias eventually. Once we have resolved them, we need to be able to cure the dielectric without shrinkage, and we have to make sure there are no thermal expansion issues. Once we build up all the layers, we have got to be able to saw it easily. And the dielectric ends up being the protective layer.”

The various test products, ranging from wireless chips to high-end DSPs, have passed thermal stressing and drop tests.

“Over the last year and a half, we fixed the fundamental issues with the material properties," he said. "That allowed us to pass reliability for packages with between one and six layers of redistribution."