How to Detect Non-Overlay Misalignment Errors?

Laura Peters, Editor-in-Chief -- Semiconductor International, 5/8/2008 8:35:00 AM

Engineers at Semiconductor Manufacturing International Corp. (SMIC, Shanghai) were confronted with an unusual problem in their DRAM fab — how to detect a misalignment error that was not caused by an overlay problem. A 5-15 nm misalignment between the active area occurred with the underlying deep trench (Fig. 1), causing an average of 5% failure. If caused by overlay errors, it could have been detected with overlay metrology tools, but this error, with the defect signature shown in Figure 2, would typically not be caught until wafer probe. The failure signature followed the first lowest die in the 3 × 2 mask shot.

2. Typical defect map of the active area using darkfield inspection on the Complus-3T tool.

SMIC's Sean Huang worked with Applied Materials’ (Santa Clara, Calif.) Amiad Conley and coworkers to detect this defect using a darkfield inspection tool, which was verified by SEM defect review and FIB cross-section. Defect inspection, which relies on die-to-die comparisons, caught the defect because of the offset in alignment between neighboring die. Conley reported on the use of darkfield inspection to catch such systematic errors at the Advanced Semiconductor Manufacturing Conference (ASMC) this week in Cambridge, Mass.

Darkfield inspection uses a larger spot size than brightfield, leading to a great depth of focus. While brightfield would typically image around one memory cell, the darkfield illumination spot covered 100 misaligned features. The detectors allowed multi-perspective data collection, indicating that the scattered signal was directional.

Conley said possible causes of such a misalignment could have been a scanner problem, mask registration or a pattern placement error. It turned out the cause was something much less likely: an earthquake.

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