Physical Analysis Provides Images of 45 nm
Laura Peters, Editor-in-Chief -- Semiconductor International, 5/6/2008 7:38:00 AM
From the different ways that strain is being implemented to the complexities of high-k/metal gate, the engineers at
Chipworks Inc. (Ottawa, Canada) have uncovered many physical details of the 65 and 45 nm process technologies. Yesterday, Dick James, senior technology analyst for Chipworks, provided an overview of the firm’s latest analyses at the
Advanced Semiconductor Manufacturing Conference (ASMC) in Cambridge, Mass. Among these were two 45 nm chips: the Intel Xeon and Matsushita Electric Industrial Co. Ltd. UniPhier parts.
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| 1. Intel Xeon PMOS transistor features embedded SiGe (25-30% Ge) and a replacement high-k/metal gate. (Source: Chipworks) |
For simplicity, Intel (Santa Clara, Calif.) forms the NMOS and PMOS transistors in a common trench. The PMOS uses embedded SiGe (eSiGe) with 25-30% graded germanium concentration. The contacted gate pitch is 160 nm with a gate length of ~42 nm and NiSiGe contact silicide spaced from the channel. The 1.5-2.0 HfO/ZrO dielectric has an underlying SiO2 interface of ~1.1 nm. The metal gate is a TiN/TiAl/Ta/TiN stack (Fig. 1). The NMOS transistors feature 42 nm metal gates and a TiAl gate. The silicide is NiSi with no platinum, possibly used to induce strain in the channel, according to James. The process flow involves depositing the high-k, TiN (for workfunction adjustment) and polysilicon. The dummy transistors are formed, including source/drains, silicide and contact etch-stop layer (CESL). The poly (but not high-k) is then removed, common tantalum and thick TiN are deposited, tantalum is etched from NMOS and filled with TiAl. The p and n workfunctions are controlled using a thermal treatment to form TiAlN in the NMOS (Fig. 2).
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| 2. Intel Xeon NMOS transistor uses a replacement high-k/metal gate approach and ~25 nm silicide/gate spacing. (Source: Chipworks) |
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| 3. Matsushita UniPhier 45 nm SoC has a very small contacted gate pitch (190 nm) and small gate length of ~30 nm. (Source: Chipworks) |
The Matsushita UniPhier 45 nm system-on-a-chip (SoC) part featured ~30 nm gate length, 190 nm contacted gate pitch, ~1.7 nm gate dielectric, NiSi and stress-enhanced transistors including a thin (10-15 nm) nitride CESL. “We are quite convinced that manufacturers are getting strain using very thin nitride layers,” James said. He said the device is a fairly direct shrink of the 65 nm device (
Fig. 3).
In looking across the gamut of 65 nm and the two 45 nm parts, certain commonalities exist, including advanced strain and platinum-doped NiSi. Embedded SiGe is becoming increasingly common in PMOS, as are nitride tensile and compressive stress caps. Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) appears to be using <100> orientation for PMOS mobility enhancement, and at least one company is using stress memorization by implantation. James said that SRAM cell size has become a better indicator of scaling than gate length or M1 half-pitch (Table), which is one of the reasons the International Technology Roadmap for Semiconductors (ITRS) is trying to get away from the designation of “node.”
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