Industry News
Staff -- Semiconductor International, 5/1/2008
Intel Tackles EUV Mask Cleans
One of the key challenges facing extreme ultraviolet (EUV) lithography still is the mask, particularly because its multilayer reflective stack is prone to surface contamination. Carbon and oxygen, both very prevalent elements, are highly absorptive to EUV radiation. At Sematech's Surface Preparation and Cleaning Conference in Austin, Texas, Ted Liang of Intel Corp. (Santa Clara, Calif.) opened up a discussion on EUV mask cleaning by detailing these challenges and results that Intel found in its study with Dai Nippon Printing Co. Ltd. (DNP, Tokyo).
EUV lithography is considered by many to be the most likely candidate for printing critical CMOS layers beyond the 32 nm node. Although EUV printing brings with it a >10× wavelength reduction (and thereby a straightforward resolution gain), it also requires a new mask architecture because the EUV wavelength is absorbed by most optical materials. EUV masks, therefore (as well as the rest of the optics in the system), are reflective rather than refractive.
Liang's talk focused in particular on the need to achieve zero "adders" (particles added by the cleaning process), which he noted is very difficult for mask cleaning. Showing a cross-section of a typical Intel EUV mask, he detailed the potential types of both non-cleanable hard defects and cleanable soft defects that are common within a technology that ultimately requires zero printable defects on a finished mask.
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| Problem defects include pattern defects (1), which are non-cleanable hard defects, but could be repaired; residual multilayer defects (2), which are non-removable, but can be compensated for; and cleanable ‘soft’ defects (3) such as particulates and hydrocarbons. (Source: Intel) |
EUV mask cleaning uses only a subset of the chemistries needed to clean wafers, and there are other distinctions:
- Wafer cleaning can handle particle removal efficiency (PRE) of <100%, but that's not the case for masks because yield is binary.
- Surface damage and film loss for EUV masks is as critical as it is for silicon wafers.
- EUV masks, compared with 193 nm masks, introduce new materials, including a ruthenium cap and TaN absorber.
- EUV masks are highly sensitive to oxidation and contamination.
- Because no pellicle is possible, the masks will require frequent cleaning in the fab.
- It's critical to achieve organic removal without oxidizing the ruthenium surface.
Liang showed that 100% particle removal from the 6 in. ruthenium/multilayer (Ru/ML) surface is possible, but it's very difficult to achieve zero process adders. Adder level depends on the surface type and adhesion levels. In 193 nm, quartz surfaces are "immune" to adders because of their low adhesion, and antireflective chrome surfaces have fewer adders with minimal imaging impact. But the same could not be said for EUV's Ru/ML surface, which retains more adders, and those adders impact imaging because they absorb the EUV light.
To make matters worse, because adders are organic, many adders are unremovable with additional scanning probe microscopy (SPM) chemistries. Alternatives, as Liang noted, include changing clean chemistries — ozonated water, for example, is effective for organic removal — and improving filtration to eliminate adders at the source.
— Aaron Hand, Executive Editor, Electronic Media
3-D ICs Are Cost-Driven, Evolutionary
Despite the somewhat revolutionary nature of 3-D integration at the device level, the technology is really evolutionary according to the panelists on Semiconductor International's latest webcast, "Through-Silicon Vias: Ready for Prime Time?" Phil Garrou, IEEE Fellow and consultant with Microelectronic Consultants of North Carolina (Research Triangle Park, N.C.), mapped out the evolutionary way in which the three components of 3-D ICs, through-silicon vias (TSVs), wafer thinning and wafer bonding, are being implemented. "In image sensors for digital cameras, TSVs are used without chip stacking. In the next generation, the sensors will be stacked with DSPs. Sony is stacking memory on logic in the 90 nm PS3 chip. Infineon and IBM are implementing face-to-face bonding in their SOLID technology. Samsung and others are using TSVs in memory stacking, but the vias go through the existing bond pads, so chip redesign has yet to take place to fully optimize the 3-D implementation."
Fred Roozeboom, Research Fellow at NXP Semiconductors (Eindhoven, Netherlands), said, "TSV is obviously no longer a dream. But real market penetration will take 4–5 years." He summarized the drivers as system cost, performance and form factor. The expected growth rate for 3-D ICs is impressive, from today's level of 45,000 wafers in 2008 (of various sizes) to around 4 million wafers in 2014, according to Jan Vardaman, president and founder of TechSearch International (Austin, Texas).
The proliferation of 3-D integration to a variety of applications, including DRAM or flash memory stacking, memory on logic, sensors and DSP, field-programmable gate array (FPGA), power amps for wireless LAN, communication ICs for mobile phones and many military chips, a few key technical challenges must be solved. "There's a need for low-cost thermal management solutions for many of these applications," Vardaman said. She said that thermal vias are helping and many companies are looking into the use of cooling channels, but enough real estate must be available for the channels. "Something that has been overlooked in our opinion is the test area. Everybody assumes that known good die are available, but there's work to be done on test methods so you can fully test these structures before you stack them together," she said.
Garrou presented the nine possible process sequences for 3-D ICs, depending on when the vias are introduced, how the chips are bonded (face/face, back-to-face), and the type of bond. He said metal-to-metal appears to be the most popular (Cu-Cu, Cu-Sn-Cu) bonding mode today because of its ability to provide both electrical and mechanical bonding simultaneously. Vardaman stated that the unit operations and tools are reasonably mature: it will be the cost/performance trade-off that determines the final timing per application.
Roozeboom presented NXP's roadmap for 3-D packaging and 3-D IC integration. The first- and second-generation solutions are multichip module (MCM) technologies in volume production. In the second-generation case, crude vias are defined by potassium hydroxide (KOH) wet etching. "The solder bumps here are really just there to take the heat off," Roozeboom said. By the fourth-generation solution, the passive interposer incorporates 10–20 μm TSVs with high aspect ratio (10:1), and the vias provide DC/grounding, RF signal, redistribution and thermal dissipation.
Roozeboom points out that the wide spectrum of coexisting technologies from low to high functionality and low to high density that lead to two-chip solutions, system-in-a-package (SiP), 3-D SiP, 3-D IC and system-on-a-chip (SoC). "We foresee coexistence for some time," he said. Although the industry is still too immature, standards and design tools will come quickly as the mainstream applications proliferate.
— Laura Peters, Editor-in-Chief
Applied Shifts to Dedicated Line
Applied Materials Inc. (Santa Clara, Calif.) has established a dedicated 200 mm manufacturing line at its Austin, Texas, manufacturing center to produce both new and refurbished 200 mm tools.
Curtis Vass, general manager of mature technology solutions (MTS) at Applied Global Services, said the company had earlier established all of its different products groups — etch, chemical vapor deposition (CVD), physical vapor deposition (PVD) and others — on dedicated lines that included both 200 and 300 mm tools. Last summer, the company began shifting all 200 mm manufacturing to a dedicated 200 mm manufacturing operation in Austin under the management of Todd Campbell.
The shift involved remodeling Applied facilities and moving people around internally to form a dedicated 200 mm equipment manufacturing organization that Vass said "is really coming together now."
"The goal is to gather together people with solid experience so Applied can meet the short lead-time requirements that customers have for high-quality 200 mm tools. The purpose is to ensure new and refurbished tools get the same attention and same processes. We did it for efficiency reasons to get the right economies of scale," Vass said.
Applied does not publicly provide information about the value of its refurbished tool business. At a recent SEMI event on upgrading older fabs, participants sized the refurbished tool market at ~$2B. Vass said Applied has shipped ~1000 refurbished tools since it got into the business in 1995.
"There is a lot of interest," Vass said, partly because of public announcements by logic and memory companies that plan to convert from 200 to 300 mm production. In those cases, Applied buys back its 200 mm equipment and refurbishes it, often upgrading the pollution abatement, heating and chilling systems before reselling the tool to other customers who, most often, are expanding 200 mm capacity.
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| Demand for 200 mm wafers will remain steady for the next two years. (Source: Freescale Semiconductor Inc., based on data from Gartner Fab Database Q307, iSuppli Foundry Tracker Q1 07 Public Announcements, Strategy Projections, and the ITRS Roadmap) |
Vass said other customers now see an opportunity to convert from 150 to 200 mm production for products such as power ICs, analog parts and MEMS devices. "For specific applications, in the past it was a little more cost-prohibitive if customers wanted to go to 8 in. A 6-in. line can be converted to 8 in. more easily than in the past," he said.
New demand arises from the "More than Moore" integration technology, which often occurs at 200 mm. Others are buying 200 mm tools for new opportunities, such as the thick epitaxial deposition steps needed for the power ICs used in hybrid vehicles.
While the current perception is that China accounts for much of the demand for 200 mm tools, Vass said current demand for refurbished 200 mm tools is "evenly distributed around the world."
The refurbished tool market is met both by the original equipment manufacturers, such as Applied, and a number of third-party vendors who refurbish various toolsets. While some tools continue to be made as new equipment, discontinued equipment, such as the Applied implanters, are only sold as refurbished equipment.
— David Lammers, News Editor
Metrology Gaps for Advanced Litho
It is clear from the International Technology Roadmap for Semiconductors (ITRS) that metrology will face some of the most demanding challenges that the technology has ever encountered if it is to continue contributing to the semiconductor industry's progress toward increasingly complex and application-intensive devices through 2022.
Lithography will be one of metrology's biggest hurdles, mostly in the area of advanced patterning; three different methods are currently under development to get around straightforward lithographic capabilities. These are double exposure, double patterning and spacer patterning. Because these three methods require different processing, they have different metrology needs.
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| Efforts to extend the lifetime of current lithography technology are placing extraordinary demands on technology. (Source: ITRS) |
Alain Diebold, a chair of the International Roadmap Committee's Metrology Technology Working Group (TWG) and Empire Innovation Professor of Nanoscale Science of the College of Nanoscale Science and Engineering at the University at Albany (New York) said, "With double exposure, the lithography TWG requires latent image CD metrology, which is something for which, as yet, there's no known solution. What this calls for, once the double exposure has been done, is the capability to check and see in the resist whether the exposed area has the correct CD before anything further is done. Technologically speaking, this is a tall order."
In the case of double patterning, a multilayer process results in the final pattern being smaller than what is possible to print. For double patterning to become viable, there must be a considerable improvement in overlay precision. And, again, metrology is the key.
With spacer patterning, lines are fabricated and an oxide is laid on their sides. Between those oxide sidewalls, which are extremely close together, patterning takes place. This makes the determination of spacer thickness on the sidewall a crucial need and, although there are several possible measurement avenues to approach this, considerable development work may be required.
"These measurements have never been approached at the level of precision that these processes require," Diebold noted. "There is a number of gaps in metrology technology that will have to be closed before we can address solutions." With some of the other requirements listed in the ITRS, the good news is that extension of CD-SEM and scatterometry technologies for another couple of generations seems likely.
Stress measurement is one of the new urgent requirement for front-end process metrology. "Considerable time was spent by the other ITRS groups determining what the requirements should be for stress measurement," Diebold said. "It soon became clear that the requirements for this kind of measurement technique in the lab vs. an inline technique differ. We need to know what is the mobility increase in the transistor's channel; however, since what one wants to measure is buried, the question becomes whether anything can be learned about what lies below by measuring what is above. This has been an ongoing problem since the 90 nm node, when stress-induced mobility enhancement first hit manufacturing."
The Emerging Research Materials and Emerging Research Devices TWG discussed all of the different potential transistor switch replacements. With each revision that comes out, more hurdles appear for metrology to defeat. "ERM and ERD covers a great variety of measurement needs. Everything is discussed, from new microscopy to the ability to detect spin and understand what influences it, to the ability to measure electrical properties on these very small devices, as well as measuring the impact of the nanoscale dimensions on their materials properties and subsequently on the device. In addition, the uniformity of these properties must be measured across whatever new kind of chip is manufactured," Diebold said.
A problem looming over metrologists originates from the fact that the industry is fast approaching the point at which we may begin to influence what we are attempting to measure by the simple act of measuring it. "These are fundamental questions that must be better understood as the new metrology techniques and technologies are developed," Diebold said. "What's the probability that you flip the spin while doing the measurement and you end up measuring the wrong thing? All this need to be better understood."
— Alexander E. Braun, Senior Editor
Tessera Incorporates TSVs Into Optoelectronics Packaging
In a déjà vu manner, Tessera Technologies Inc. (San Jose) recently acquired a few more smart optics and imaging companies — namely EyeSquad and FotoNation — and quickly turned out another advanced wafer-level chip-scale packaging (WLCSP) technology for image sensors and other optical devices destined for electronic products with a camera.
"Tessera's strategy is to offer miniaturization and they're going after the optoelectronics packaging arena," said Jim Walker, research vice president at Gartner (Stamford, Conn.). "They've acquired several optics companies during the past couple of years and created a bit of a niche. Now Tessera has taken Shellcase's process and minimized it again — with through-silicon vias this time — and it gives them a good handle on the technology and the market. From an optoelectronics packaging perspective, they don't have many serious competitors."
To back up a little bit, in case you haven't been following Tessera closely, they entered the consumer optoelectronics packaging market a little more than two years ago by first acquiring Shellcase (and its patented family of WLCSP technologies Shellcase OC, Shellcase OP, as well as chip-on-board Shellcase CF), followed by Digital Optics Corp. Soon after, Tessera rolled out a WLCSP technology known as "RT" for its razor-thin profile.
Tessera's latest WLCSP intellectual property (IP) offering is the Shellcase MVP (short for micro via packaging). It's an ultrathin (~500 µm) high-performance through-silicon via (TSV) solution that enables 3-D stacking with digital signal processing (DSP) or flash memory, and is compatible with reflowable wafer-level cameras.
While Tessera declined to give away its process step secrets for MVP, the unique development here is the way in which they create the via through the pad without damaging the silicon. "We managed to get away from the problems and reliability issues incorporated into the silicon die when using standard TSV processes," divulged Schlomo Oren, general manager of Tessera Israel-Jerusalem.
MVP's basic process steps are very similar to those of the RT. The design rules feature a scribe line width of ≤100 μm, bond pad size of ≤50 μm and bond pad pitch of ≤110 μm. As far as metallization and routing go, the MVP has direct contact to CIS, through pad T-contact via, no process in the scribe line, and no special design mask is required by the image sensor fabrication facility.
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| MVP’s general process steps. (Source: Tessera) |
A JEDEC moisture sensitivity level (MSL) reliability rating of 1 means that MVP can be used in harsh environments, such as automotive ones. "We've run extensive tests on this device, in excess of 4000 cycles [requirement is only 2000 cycles: -40 to 125°C] without failures," Oren noted. "We're very confident about the reliability of this package, which should be attractive to the automotive industry because its reliability requirements are much higher than standard consumer optics.
"Another benefit of MVP is that it uses existing manufacturing infrastructures in the market," Oren said. "This will significantly shorten the shift from technology introduction to high-volume manufacturing. In such a dynamic market, it's extremely important to minimize the time between technology introduction and new product availability."
MVP is offered in both cavity and non-cavity formats, with leaded or lead-free bumps, and is available for licensing from Tessera.
Zooming in on the WLCSP market, analysts have been predicting a bit of a slow migration from wire bonding and flip-chip to WLCSP. "We're seeing an increase in the adoption of wafer-level packaging in general," Walker said. Gartner, for example, predicted last year that the total WLCSP market would progress from 8905 millions of units in 2007 to 11,974 millions of units in 2011. The image sensor segment of the market is also expected to be one of the faster growing segments, with an estimated 15.3% compound annual growth rate between 2006 and 2011.
Prismark (Cold Spring Harbor, N.Y.), an electronics consulting firm, projected last year that by 2011 WLCSP will encompass 50% of the market, while wire bonding and chip-on-board will slip to 40% and flip-chip cavity and others will hang on at 10%.
— Sally Cole Johnson, Contributing Editor
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