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Self-Aligned Barrier Improves Interconnect Reliability

A new PECVD self-aligned barrier using a germanium dopant offers a simple, cost-effective means of improving electromigration resistance of copper interconnects.

H.J. Wu, J. O'loughlin, R. Shaviv, M. Sriram, K. Chattopadhyay, Y. Yu, T. Mountsier, B. van Schravendijk, S. Varadarajan, G. Dixit and R. Havemann, Novellus Systems Inc., San Jose -- Semiconductor International, 5/1/2008

Meeting the ever-increasing electromigration (EM) requirements in copper interconnects is becoming more difficult as Moore's Law progresses. As line dimensions shrink, critical void size for EM failure is also reduced, causing a sharp decrease in mean time to failure (MTTF).1 The International Technology Roadmap for Semiconductors (ITRS) stipulates that continued scaling requires an increase in operational current density.2 Therefore, a significant improvement in EM resistance is required to enable continued scaling.

The interface between dielectric diffusion barrier and copper has been shown to be the main path for copper diffusion and the weakest link in resisting EM failure.3,4 Many approaches have been explored to improve, for instance, the silicon carbide (SiC)-based/copper interface. Selective deposition approaches, including selective metal caps and self-aligned barriers, have received significant attention.5–10 The implementation of a selective metal cap, such as CoWP, is challenging because of the difficulty in achieving good selectivity on copper vs. dielectric surface, which may lead to degraded dielectric reliability.9,10 This approach also entails added processing steps and increased cost.

A self-aligned dielectric barrier, on the other hand, has good deposition selectivity and may be achieved through a modification to the dielectric diffusion barrier unit process without degrading the electrical isolation characteristics of the intra/intermetal dielectric layers.5–7 Furthermore, a self-aligned barrier may be optimized to yield an improvement in the reliability of the damascene structure by strengthening the SiC/copper interface.5

Self-aligned barrier

The plasma-enhanced chemical vapor deposition (PECVD) self-aligned barrier (PSAB) has recently attracted attention because of its high selectivity, low cost of implementation and benefits to interconnect reliability. In this process (Fig. 1), the residual copper oxide (CuOx) after chemical mechanical planarization (CMP) is first reduced using plasma pre-treatment. This step helps ensure a good interface between the copper and SiC, and encourages uniform chemical doping of the copper surface.11 Next, the copper is exposed to a gaseous ambient containing the dopant. Silicon doping of the copper with exposure to silane (SiH4) has been reported.5–7 Concentrations of the dopant in the ambient and process temperature are key variables in controlling the dopant level. In the next RF pinning step, reactive gases scavenge the unreacted chemicals from the process cavity, and may also be used to chemically alter the composition of the doped copper surface prior to SiC deposition. The SiC-based CVD step completes the sequence of dielectric barrier or etch-stop formation. All of these steps may be processed in situ and/or sequentially in a Vector PECVD system.

1. Pre-treatment reduces the copper oxide, doping introduces silicon or germanium, RF pinning uses reactive gases to scavenge unreacted chemicals, and then the SiC-based barrier is deposited.

Germanium doping

Germanium has long been recognized as one of the chemicals of choice for these applications. Recently, a novel technique for Ge-PSAB was developed.11 Control of the doping profile with chemical inside the PECVD chamber is generally difficult, particularly at a high temperature. Temperature strongly influences the reaction between the chemical and copper surface and resulting dopant diffusion into copper (Fig. 2a).

2. Copper resistance increases with process temperature (left). Control of germanium doping with optimization of the ‘exposure factor’ (right).

Higher process temperature may lead to excessive germanium doping and an increase in copper resistivity. However, higher temperature (~350–400°C) is generally needed for high-quality SiC deposition. The platform's multiple station sequential deposition architecture allows for flexibility in using different process temperatures for the substeps needed for the PSAB process. RF pre-treatment and chemical doping may be conducted at a lower optimal temperature, followed by SiC deposition at a higher temperature, providing controlled doping and better SiC film quality. Higher throughput is achieved by partitioning the process steps. Germanium doping is further modulated by optimizing an "exposure factor" (Fig. 2b). A two orders of magnitude range of the germanium doping level at the copper surface can be achieved by optimizing temperature and exposure factor. Figure 3 shows the SIMS depth profile analysis of the optimized dopant distribution.

3. Germanium dopant profile at the surface of the copper film.

4. TEM of a trench corner following the germanium self-aligned barrier (Ge-PSAB) treatment and SiC deposition.
High selectivity of the PSAB process arises through differences in reactivity and reaction products of the gaseous constituents with the copper and dielectrics. In the case of silicon-based PSAB, SiH4 exhibits a thermally activated reaction with copper, but the reaction on the dielectric surface results in the formation of an insulating film. Similarly, germanium rapidly reacts with copper, as shown in the SIMS analysis, but electrical testing shows no degradation of dielectric reliability caused by germanium's reaction to dielectric films. The TEM in Figure 4 of the structure with Ge-PSAB/SiC also shows no evidence of any additional layer at the interface of SiC with the low-k dielectric.

Process integration, reliability

We conducted process integration testing of the Ge-PSAB process using 65 nm node features and a dual damascene scheme with Coral bulk low-k dielectric. Two metal layer damascene structures were used for reliability investigation. Comb capacitor line-to-line dielectric breakdown data collected from test structures with 80 nm spaces showed that Ge-PSAB and the control processes provide a statistically equivalent breakdown performance (Fig. 5a). The distribution of the dielectric breakdown is tighter for the Ge-PSAB split than that of the control, with normalized Weibull b values of 0.27 V-1 and 0.17 V-1, respectively. A low line-to-line leakage is also observed for the Ge-PSAB process (Fig. 5b). These dielectric isolation strength results demonstrate the excellent selectivity achieved with this technology.

5. Normalized line-to-line dielectric breakdown for comb capacitors with 80 nm line spacing for the control (white) and the Ge-PSAB (orange) splits (left). Line-to-line leakage for comb capacitors with 80 nm line spacing for the control (white) and the Ge-PSAB (orange) splits (right).

It has been reported that high-temperature CuSi formation with SiH4 exposure in the PECVD process chamber leads to a degradation in stress migration (SM) performance of the copper/low-k interconnect structure.12 To investigate the SM performance of this process, via resistance shift of two-level metal plate over metal plate structures was measured after a 168-hour-anneal at 200°C. The result suggests no degradation of SM performance with Ge-PSAB compared with the control samples (Fig. 6a).

6. Normalized stress migration failure rate for Kelvin via testers with wide M2 strap over wide M1 strap connected by a single via (a). Downstream electromigration time to failure for the control (white) and Ge-PSAB (orange) splits. A sevenfold increase in MTTF (t50) is measured (b).

Package-level EM performance of the Ge-PSAB and control samples was compared using a standard single-link via-terminated test structure. Significant improvement in MTTF for the downstream test is noted with the integrated Ge-PSAB scheme, as compared with the control (Fig. 6b). The improvement in MTTF shows the intrinsic potential for Ge-PSAB to improve EM performance.

Details of the mechanism for EM improvement are still under investigation. It is possible that the multi-step Ge-PSAB process addresses reliability enhancement by tackling several failure modes simultaneously. We previously reported time-dependent dielectric breakdown (TDDB) improvements associated with improved adhesion of the SiC to both copper and low-k dielectric, enabling better encapsulation of the copper inside the trench.5 In this work, adhesion energy measurements for both the control and germanium/copper interfaces are measured to be high and similar. The distribution of the germanium inside the copper (Fig. 3) shows a higher concentration near the Cu-SiC interface, where a CuGex (x<10 %) solid solution is at equilibrium.13 The thin layers of CuGex may aid to prolong the growth of nascent defects (voids) within the interconnect structure. In addition, cladding layers around the copper surface create a shunt layer around the lower-resistivity conducting metal, diverting and pushing the current from the interface further into the copper matrix. Diffusion of copper with the electron wind would disturb the metallurgical equilibrium of the CuGex/Cu structure because of an increase in the concentration of germanium in copper-depleted areas near the interface. This creates a net force, proportional to the concentration gradient; opposing EM according to:

This mechanism for EM improvement is further supported by the observed "self-repair" effect during the EM test of these Ge-PSAB samples. Typically, EM is characterized by either an abrupt or smooth and continuous increase in line resistance. With the Ge-PSAB, a small increase in line resistance was often found to repair itself during testing, indicating sealing of voids during the test. A recent measurement of the current acceleration coefficient, n, shows n=1.2 for downstream EM with Ge-PSAB, significantly lower than n=1.6 measured for the control. Thus, it may be hypothesized that the "self-repair" phenomenon renders lines treated with Ge-PSAB relatively less sensitive to current density. Measurements of activation energy for EM with Ge-PSAB are in progress, and preliminary results indicate values that are comparable to or ~5% higher than those measured using the control dielectric barrier scheme.

Conclusions

A novel PECVD PSAB process using germanium dopant provided an improvement in EM resistance with no degradation in SM or dielectric reliability. Control of germanium doping concentration and profile was achieved at low doping temperatures and optimal exposure conditions. Further process optimization is in progress, as this technology offers a potentially cost-effective solution to improve the EM performance of current and future copper interconnects.


Author Information
Hui-Jung Wu is currently a senior technologist with the Process Applications Group at Novellus Systems. Prior to Novellus, he was with Intel and Honeywell. He holds a Ph.D. in chemistry from Rensselaer Polytechnic Institute (Troy, N.Y.), and has over 15 publications and 21 granted U.S. patents.


References
1. C.-K. Hu et al., "Effects of Overlayers on Electromigration Reliability Improvement for Cu/Low-k Interconnects," IRPS, 2004, p. 222.
2. ITRS reports.
3. V. Sukharev, E Zschech and W.D. Nix, "A Model for Electromigration-Induced Degradation Mechanisms in Dual-Inlaid Copper Interconnects: Effect of Microstructure ," J. Appl. Phys., 2007, Vol. 102, p. 3505; E. Zschech et al., "Reliability of Copper Inlaid Structures — Geometry and Microstructure EffectsE," Proc. of the Adv. Metal. Conf., 2002 (unpublished), p. 305.
4. J.R. Lloyd et al., "Electromigration and Adhesion," IEEE Trans. of Device and Materials Reliability, 2005, Vol. 5, No. 1, p. 113.
5. K. Chattopadhyay et al, "In-Situ Formation of a Copper Silicide Cap for TDDB and Electromigration Improvement," IRPS, 2006, p. 128.
6. Y. Hayashi et al., "High Performance Ultra Low-k (k=2.0/keff=2.4) Hybrid Delectrics/Cu Dual-Damascene Interconnects With Selective Barrier Layers for 32 nm Node," Proc. of the Adv. Metal. Conf., 2006, p. 37.
7. T. Usami et al., "Highly Reliable Interface of Self-Aligned CuSiN Process With Low-k SiC Barrier Dielectric (k=3.5) for 65 nm Node and Beyond," Proc. of IITC, 2006, p. 125.
8. W.S. Shue, "Evolution of Cu Electro-Deposition Technologies for 45 nm and Beyond," Proc. of IITC, 2006, p. 175.
9. J. Gambino et al., "Effect of CoWP Capping Layers on Dielectric Breakdown of SiO2," IPFA, 2007, p. 59.
10. J. Gambino et al., "Reliability of Cu Interconnects With Ta Implant," Proc. of IITC, 2007, p. 22.
11. USA Patent application 10/980,076, to be issued June 11, 2008.
12. M.-S. Yeh et al., "Effect of Cu Line Capping Process on Stress Migration Reliability," Proc. of IITC, 2006, p. 113.
13. B. Predel, Group IV Physical Chemistry - Phase Equilibria, Crystallographic and Thermodynamic Data of Binary Alloys, Volume 5 - Electronic Materials and Semiconductors, O. Madelung, ed., Landolt-Bornstein, Springer-Verlag, 2006.
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