3-D Interconnections On the Rise

There are a number of compelling and interrelated reasons for making 3-D interconnection structures. For example, one of the most obvious features of finished 3-D structures is that they are highly dense. With a shorter signal path, transmit power requirements become less because signal loss is reduced, thus either performance is improved or, in the case of portable electronics, battery life is extended. It also means that less materials and energy are used in construction, which impacts both cost and long-term sustainability. Given the increased sense of general urgency relative to energy and material use on a global basis, 3-D structures help contribute to the conservation effort, even if only in a small way.

A wide range of interconnection solutions are being brought to bear on the challenge, beginning at the wafer itself. An indication of this wafer-level interconnection focus can be seen in the surge of interest in through-silicon via (TSV) technology. It is increasingly being considered as a necessary interconnection solution, both for stacking of wafers and chips for IC package assemblies. TSVs should complement the various flip-chip and wire-bonded stacked chip solutions that have been at the forefront of the recent 3-D technological charge. Other stacking solutions, including stacked package or package-on-package (PoP), are being used in concert with stacked chips to create assembled IC devices with even more functionality within a given footprint. These solutions are, in fact, now being generally positioned and accepted as preferred system-in-a-package (SiP) alternatives to the pursuit of system-on-a-chip (SoC) owing to SoC expense and lead time. In contrast, SiP offers significant flexibility to the product developer.

Moving forward, 3-D integration of IC package technology into next-level interconnections and assembly opens the door to another entire universe of opportunity. For example, the embedment of ICs and/or IC packages into substrates, is being proposed for so-called Occam-type processing, where copper circuits are plated making connection directly to component leads. The method now in early development could obviate the need for electronic assembly using high-temperature lead-free solder and all of its other risks, such as tin whiskers. There is also possibility to integrate higher-level ESD protection into the IC package being explored. This will take a significant burden off of the chip, releasing untapped performance potential by reducing power requirements both at I/O and core level. Other 3-D opportunities now in the R&D phase include direct-path interconnection of high-speed signals over the top between chip package assemblies, completely bypassing the PCB with its inherent problems. It is now reasonable to expect that the benefits of thoughtful electronic interconnection design can be extended throughout the entire hierarchy of electronic system elements.

However, the technologies that support interconnection must also adapt to the challenge. In a 3-D world, everything from design tools to manufacturing and assembly to testing equipment will need to adapt to the new concept where electronic assemblies will require interconnection on more than one surface. Given that active elements in a room-size router or mainframe computer comprise perhaps a single cubic centimeter, it is clear that the electronics industry has a ways to go to achieve the highest possible efficiency in electronic interconnections, leaving the door wide open to a future of ever more thoughtful and clever solutions. 3-D interconnection will be key.