Package-on-Package Variations On the Horizon
Improvements to both the surface-mount process and PoP assembly process and materials set are becoming necessary as the industry embarks on high-volume production of next-generation PoP devices.
Flynn Carson, STATS ChipPAC Inc., Fremont, Calif. -- Semiconductor International, 5/1/2008
When Apple’s iPhone debuted in 2007 and teardowns were immediately featured and available seemingly overnight, package-on-package (PoP) technology was prominently on display for all to see. PoP had finally made it to the limelight. However, PoP has been building steam for quite some time, and is now the package of choice to combine mobile phone processors with memory for more advanced mobile phones.
Steadily over the past few years, all of the major handset makers have shifted to the PoP configuration as the engine to power their flagship products. The reasons why are related not only to size and performance, which is immediately apparent at first glance, but also to business and supply chain issues that may not be so obvious. The future for PoP continues to look bright, as it is being implemented into many new products that require increased performance, smaller form factors, and different memory configurations and interfaces. PoP variations are quickly being developed and applied to meet these ever-increasing demands. As the PoP format has proven itself and matured, other applications besides mobile phones are beginning to reap the benefits of PoP.
Texas Instruments (Dallas) and Nokia (Helsinki, Finland) should be noted as the first to realize the potential of PoP and to implement into mass production. There have always been memory and processors on printed circuit boards (PCBs) in mobile phone handsets. In the past, these devices were packaged separately and side by side. The increasing amount of memory required to drive the latest feature-rich applications that consumers are demanding in their mobile phones is fueling the need for stacking memory devices in the same package size and form factor. This approach was enormously successful and, as a result, on average there is at least one stacked die package shipped in every mobile phone today; this trend is increasing.
It seems reasonable to stack the memory on the logic processor to realize even greater scale of miniaturization, performance and cost-effectiveness. However, what seems logical is not so simple. Because the logic processor is the higher value device in a logic plus memory configuration or stack, the logic device manufacturer is expected to carry the burden of integrating or stacking the memory to add value. Most logic device manufacturers, however, encountered great difficulty in integrating memory devices with their logic devices. They were expected to buy memory in wafer form, and were liable for test yield, interaction and quality issues relating to the memory device, which was not their silicon. In addition, testing memory is a specialty best left to memory manufacturers, and providing access to properly test the memory device created unexpected complexity and cost. After initial ill-fated attempts, most logic manufacturers who attempted such logic plus memory integration in the same package were anxiously seeking a better approach.
The PoP solution
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| 1. PoP integrates logic and memory in the same package. |
Handset manufacturers don’t have to carry the inventory of a specific logic plus memory combination as they would if it was integrated into a stacked die package. The flexibility to configure top memory packages with bottom logic packages was enabled by a JEDEC standard governing the ball-out of the top PoP, both electrically (based on memory configuration within) and mechanically. The bottom package is also governed by a JEDEC mechanical standard. This standardization really opened the door to allow manufacturers to design and produce products that would be compatible with each other, and is a fundamental reason why PoP has matured and been launched into high-volume manufacturing over the past few years.
The implementation of PoP into volume production today has not always been an easy road. As with all new packaging technologies, there were barriers that had to be overcome. To realize the configuration flexibility of PoP, the package stack had to be configured and reflowed simultaneously to the PCB. This was not commonly done before, so it had to be developed and optimized by the handset maker or its electronic manufacturing service (board mount) provider. Not only was reflowing two ball grid array (BGA) packages on top of each other new, but reflowing two very thin, fairly large, fine-pitch BGAs also proved to be something of a challenge. Because both packages are relatively fine pitch (typically 0.65-mm pitch or less for package-to-package connection), the amount of warpage that each package can have during the reflow process is quite limited. Previously, package warpage during the reflow process was not a major concern that affected surface-mount yields.
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| 2. The periphery of the bottom PoP is devoid of any molded encapsulant material to enable interconnection of the top package. |
Controlling the warpage of the top package is a challenge as well. The top PoP can have 2-5 die stacked within. These devices have various sizes; some are of the same or similar size requiring the use of spacers in between the stacked die to enable the wire bond to the substrate. While the bottom PoP typically has a concave shape when viewing the top of the package during reflow, the top PoP can have either a concave or convex shape. Despite the top PoP having molded encapsulant material extending to the package edge that usually results in less warpage than the bottom PoP, the top PoP warpage must often be tailored to that of the bottom package or held tighter to allow for higher warpage in the bottom package. Optimization of package materials and thickness is just as important for the top PoP to produce acceptable surface-mount yields. Warpage targets for the top and bottom package during reflow were initially on the order of 80 µm. However, with more study, some customers have decreased the warpage target to as little as 60 µm for a 0.65 mm package-to-package interconnect pitch.
Current PoP trends, improvements
The current trend is toward smaller and higher-density PoPs with 0.5 mm package-to-package interconnect pitch. The requirement for such packages will be as low as 50 µm warpage during reflow. Such packages will also be moving to 0.4 mm ball pitch on the bottom of the bottom PoP because of the high pin count and restricted package area (generally, the target is 12 × 12 mm or smaller package size), thus requiring coplanarity specifications to be met at room temperature and tight warpage specifications to be met at the temperature above the solder melting point during reflow. On the surface-mount side, to help enable the mounting and simultaneous reflow of PoPs with finer ball pitches, improvements to the surface-mount process are being introduced. The typical surface-mount process today includes printing paste on the PCB, placing the bottom PoP, dipping the top PoP balls in flux, placing the top PoP on the bottom PoP and running them through furnace reflow in clean dry air. New processes being introduced include dipping the top package balls in solder flux or solder paste to improve the robustness of the top-to-bottom package connection during reflow.
Improvements to both the surface-mount process and PoP assembly process and material set will be necessary as the industry embarks on high-volume production of next-generation PoP devices. Most bottom packages in production today leverage wire-bond interconnection. However, flip-chips can generally accommodate the higher density and performance requirements of the next-generation while still meeting the 12 × 12 mm or smaller package size requirement (Fig. 3). Thus, most bottom PoP logic devices on the drawing board are flip-chip devices. Another advantage of flip-chips is that the mounted height of the flip-chip device can be less than that of an encapsulant molded wire-bonded device. The flip-chip device does not need to be encapsulant molded, which also reduces the tooling cost. Yet, the absence of mold encapsulant material and the need to underfill the flip-chip device creates challenges in controlling the package warpage.
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| 3. Flip-chips can accommodate higher densities and performance requirements of the next-generation PoP while meeting smaller package size requirements. With flip-chips, the mounted height of the device can be less than that of an encapsulant-molded wire-bonded device. |
Controlling package warpage
Thicker substrates and new packaging materials are being qualified to control package warpage. The flip-chip die can be thinned to meet the maximum mounted height of 0.22 mm (per JEDEC mechanical guideline) to allow for a top PoP of 0.5-mm pitch to be mounted on top. Other bottom PoP variations are also being developed to help control the package warpage and allow for thicker die. Flip-chip bottom packages with encapsulant mold compound on the top center of the package or extending to the package edge are being developed. These packages typically have build-up contacts at the top periphery lands (solder on pad or other schemes) to help “bridge the gap” to the top PoP. Such “bridging” schemes are also being employed for bottom packages with two die stacked within. Some advanced next-generation PoPs require logic plus logic or logic plus analog stacked within. The bottom die in such a stack can be either flip-chip or wire bonded, but the top die is invariably wire bonded. Thus, encapsulant molding is required and, unless 0.65-mm top PoP ball pitch can be used, “bridging” schemes are necessary.
Reducing height
One of the most difficult challenges faced by the PoP today is to reduce the stacked height. Presently, the PoP is typically the thickest package within the digital section or side of the PCB within the mobile phone. While other packages, including stacked die packages, can achieve 1.2 mm maximum or less package height, the PoP stacked height struggles to meet 1.4 mm maximum height. Early PoP stacks were in the neighborhood of 1.8 mm maximum height and current PoP stacks are in the 1.6 mm maximum-height range. The difficulty in reducing the stacked height lies in reducing the height of the mounted device or encapsulant mold of the bottom package and the gap required between packages. Reduction of this thickness can create higher warpage, as previously discussed. Reducing the top PoP is possible, but it already uses the thinnest substrates and die thickness in mass production (0.13-mm-thick substrates and 75-60-µm-thick die). Further reduction requires even thinner substrates, die attach materials (die attach films), and die thickness of 60 µm and below. The cost of these materials is often offered as a premium, and the handling of such thinner materials and devices in production can be problematic. In the past year, new PoP solutions have been introduced that stack two memory devices in the top PoP while still meeting the 1.4 mm maximum-height requirement. In the future, such PoP stacks will be able to meet 1.2 mm maximum height with very thin memory die thickness and advanced thinner packaging materials.
Future of PoP
On the horizon are new PoPs or variations to address some of the weak points of the current conventional PoP. For instance, one way to address the challenge of controlling PoP warpage as the packages get thinner with finer ball pitch is to mount the top and bottom package together prior to mounting on the PCB. Although this defeats one of the primary advantages of the flexibility of PoP, “pre-stacking” it prior to board mount is a relatively straightforward process with one less variable to control during the reflow process — the warpage of the PCB itself during reflow. Testing of the pre-stacked PoP can assure it is good and exhibits much lower warpage than the top and bottom PoP do separately, thus making PoP similar to mounting a more conventional fine-pitch BGA on the PCB. The pre-stacked PoP is particularly attractive to device manufacturers who can now provide both the bottom logic and top memory PoP to the end user. This option is attractive to those end users who are not in the mobile handset space, but are looking to use PoP for their applications.
As the performance and capability of the processors in the bottom PoP increase, the die tends to grow in size, even as the wafer fabrication geometry shrinks from 90 to 65 nm and below, making it difficult to fit the device in a 12 × 12 mm or smaller package that is desired today. Fan-in PoP solutions (in which the lands on the top surface of the bottom PoP are not peripheral, but are in the center) have been developed to enable smaller, higher-density PoP devices with larger die-to-package ratios (Fig. 4). Fan-in PoPs also enable the stacking of a smaller, more cost-effective center BGA top PoP. Because the mold encapsulant or top surface of the package extends to the package edge, this type of package has demonstrated less warpage than a conventional PoP solution. Another advantage of fan-in PoP is the ability to accommodate a higher number of interconnects to the package stacked on top. This can be achieved without growing the package because the top center interconnect array can be 0.5 mm or even 0.4 mm pitch. This allows processor-to-processor package stacking or processor-to-high-pin-count memory interfaces that will be a key technology for handset makers. In a sense, PoP variations such as fan-in PoP are filling the role that embedded device in substrate and fan-out wafer-level packaging approaches are targeting to fill in the future.
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| 4. Fan-in PoP solutions enable smaller, higher-density PoP devices with larger die-to-package ratios. They also enable the stacking of a smaller, more cost-effective center ball grid array top PoP. Because the mold encapsulant or top surface of the package extends to the package edge, this type of package is less prone to warpage than conventional PoP solutions. |
Conclusion
PoP has truly arrived as a packaging format that will be a mainstay for combining processor and memory in mobile phones for years to come. Many new products will be released using PoP, and new variations of the PoP will be introduced to meet the demands of smaller size, lower height, higher performance, and finer ball pitch and pin count. Improvement and introduction of new materials will help reduce package warpage problems, and new surface-mount techniques will help realize acceptable board-mount yields. PoP is expanding beyond the mobile phone application into other handheld devices and memory storage applications and this trend is likely to continue. Therefore, PoP will continue to be at the forefront of 3-D packaging innovation.
| Author Information |
| Flynn Carson is STATS ChipPAC’s vice president of 3-D packaging, responsible for new product and technology integration. He has more than 18 years of experience in the packaging industry supporting production and developing new products. Carson received a B.S. in mechanical engineering and materials science from the University of California, Davis. |
