SEMI Event Blends Nostalgia With a Look to the Future
Alexander E. Braun, Senior Editor -- Semiconductor International, 4/2/2008 8:04:00 AM
SEMI (San Jose), in conjunction with the Chemical Heritage Foundation (Ashland, Ohio), held the first part of their two-day event, “Empowering the Silicon Revolution — The Past, Present, and Future of the Semiconductor Equipment and Materials Industry,” at the Computer History Museum (Mountain View, Calif.).
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| Arthur Zafiropoulo, Chairman, Ultratech |
“When we consider wafer size transition, we see that some 70 companies were involved in 200 mm and about 30 in 300 mm. This is because everything is getting extremely expensive; the cost of building fabs is increasing substantially, which in turn limits the number of players. As we look at the projections for 450 mm, there are only two or three. To justify building a 450 mm fab, its cost has to be multiplied two or three times per year of sales. So if a fab costs $5B, an output of between $10 and $15B is needed. If you have only two companies that can afford this, do you have a fab in Japan and another in Taiwan, with the [seismic] fault problems they have? What about the risk factors for customers — are they going to buy from one factory? I believe that fab diversification is necessary; you need locations not only in Taiwan or Japan, capacity must be distributed to reduce the risk factors of earthquakes or tornados. But with only two companies being able to afford it, you cannot build fabs in Ireland and Israel as well.”
“It took about five years to ramp 125 mm to production in 1981, six years to ramp up 150 mm, eight years to get to 200, 13 to get to 300 mm, and 27 years for 450 mm if it enters into pilot production in 2020, but it will probably take more than that. Wafer size transitions are becoming longer and more expensive. The total development cost for 300 mm came to between $10 and $12B. Extrapolated to 450 mm, this means it may require about $100B. The ROI scenario does not look good.”
“There is increasing cost pressure on the IC manufacturer. For example, gate cost scaling is dropping; the cost per gate is about six microcents. This means that the gain of going to smaller features is declining; thus, continuing to go to smaller dimensions may not be the direction of the future — another reason to wonder who is going to fund 450 mm. Meanwhile, the actual cost of device design is rising considerably and design starts by feature size are decreasing. There will be fewer designs per node, leading to a higher volume of wafers per node and more flexibility.”
“Fewer designs in the marketplace means that now foundries have a chance to catch up in technology to the IDMs. TSMC announced that over the next few years they will invest $5B in R&D to go from 32 to 22 to 15 nm structures. However, this also means that that smaller players will have less of a chance, because if you come up with a better idea for a garage door opener, the large fabs will not want to talk to you because the market is too small. You will have to have a very large market before TSMC, UMC, SMIC or Chartered take notice. The smaller companies with the new ideas will not be successful because no one will want to build their chips.”
“The larger companies, such as Texas Instruments and AMD are going fab-lite, but the foundries they’re going to are not spending any money. The foundries are waiting for companies like Qualcomm to ask for 20,000 more wafer starts per month, and they will then say, ‘We can do that for you. Do you have $1.5 B to help us build a new fab?’ The fabless guys think that they’re really fabless because they don’t own a fab, but they are not. Financially, they are or will be in the fab business very soon.”
“Projections for foundry spending show a considerable decrease. In 1998, they spent ~80% of their sales in capex equipment; that is not sustainable. Today, they are spending about 20%, and it will probably stabilize at that level.”
“By 2011, 60% of the industry will be <130 nm structures, and all memory will be <65 nm technology. TI is building a factory in the Philippines for packaging, they have invested more than $1B, and it is going to be a 200, not 300 mm fab. Last year, they spent more money in the back end than in the front end. They believe that this is a key differentiator — the back end and packaging will be the differentiator.”
“Today, we build transistors on x and y, one plane. We will begin building in 3-D. This will create an acceleration of Moore’s Law, and it will go from 18 to 12 months — for NAND flash, not for logic. The driver will be NAND flash.”
“Particularly with 300mmPrime, 300 mm wafers should have a life expectancy of 22 years.”
Finally, with tongue firmly planted on cheek and calling special attention to the date, Zafiropoulo predicted: “The first 450 mm wafer will be introduced April 1, 2020, at 3:30 p.m. PST.”
