3-D ICs Are Cost-Driven, Evolutionary
Laura Peters, Editor-in-Chief -- Semiconductor International, 3/31/2008 9:39:00 AM
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| 1. This eight-chip stacked flash memory device is ~30% thinner than the pre-thinned stacked thickness. (Source: Samsung) |
The proliferation of 3-D integration to a variety of applications, including DRAM or flash memory stacking, memory on logic, sensors and DSP, field-programmable gate array (FPGA), power amps for wireless LAN, communication ICs for mobile phones and many military chips, a few key technical challenges must be solved. “There’s a need for low-cost thermal management solutions for many of these applications,” Vardaman said. She said that thermal vias are helping and many companies are looking into the use of cooling channels, but enough real estate must be available for the channels. “Something that has been overlooked in our opinion is the test area. Everybody assumes that known good die are available, but there’s work to be done on test methods so you can fully test these structures before you stack them together,” she said.
Garrou presented the nine possible process sequences for 3-D ICs, depending on when the vias are introduced, how the chips are bonded (face/face, back-to-face), and the type of bond. He said metal-to-metal appears to be the most popular (Cu-Cu, Cu-Sn-Cu) bonding mode today because of its ability to provide both electrical and mechanical bonding simultaneously. Vardaman stated that the unit operations and tools are reasonably mature: it will be the cost/performance trade-off that determines the final timing per application.
Roozeboom presented NXP’s roadmap for 3-D packaging and 3-D IC integration (Fig. 2). The first- and second-generation multichip module (MCM) technologies are in volume production. In the second-generation case, crude vias are defined by potassium hydroxide (KOH) wet etching. “The solder bumps here are really just there to take the heat off,” Roozeboom said. By the fourth-generation solution, the passive interposer incorporates 10-20 µm TSVs with high aspect ratio (10:1), and the vias provide DC/grounding, RF signal, redistribution and thermal dissipation.
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| 2. With each new implementation, interconnect density is increased. A passive interposer is used throughout. (Source: NXP Semiconductors) |
Roozeboom points out that the wide spectrum of coexisting technologies from low to high functionality and low to high density that lead to two-chip solutions, system-in-a-package (SiP), 3-D SiP, 3-D IC and system-on-a-chip (SoC). “We foresee coexistence for some time, which will depend on the application, cost, performance and form factor,” he said. Although the industry is still too immature, standards and design tools will come quickly as the mainstream applications proliferate.
