‘First-Time-Right’ Recipe Optimization for Wafer Inspection
A methodology for developing a brightfield wafer inspection recipe involving tight coupling with a review SEM resulted in improved capture rate of critical defects from a previously employed process of record, substantial time savings in recipe optimization and first-time-right results.
A. Stamper, S. Chong and K. Nafisi, IBM, Hopewell Junction, N.Y., www.ibm.chips.com; P. Feichtinger, W.T. Chia, D. Randall and A. Khullar, KLA-Tencor Corp., San Jose, www.kla-tencor.com -- Semiconductor International, 4/1/2008
Not only is “first-time-right” a requirement in today’s IC fabs, but capture rates for critical yield-limiting defects need to be maximized while false and nuisance counts need to be minimized. The traditional brightfield (BF) recipe optimization process involved adjusting several inspection parameters, necessitating multiple iterations between the BF inspector and SEM review tool. Approaching recipe entitlement in this manner takes too long for a production environment given the number of optics modes and the realities of queue times and other limitations.
We present a method and toolset that supports reaching this recipe optimization goal in a novel way by tightly coupling the review SEM into this process. Implementation in an IC fab resulted in a dramatic improvement in capture rate of critical defects from the previously employed process of record, as well as substantial time savings in recipe optimization.
Best practices
Shrinking design rules, smaller defect types, additional noise sources and new process integration schemes create significant challenges for effective inline wafer inspection methodologies. Yield enhancement best practices are typically driven by characterizing the magnitude of yield-limiting defects detected inline and their effect on inline and final test yields. The magnitude of specific yield-limiting events often determines the priorities of yield, integration and process engineering teams. Effective inline defect inspection acts as a monitor of the health of the line, a means for improvement of yield, as well as work in process (WIP) protection from potential excursions. It is absolutely critical, therefore, that the inline inspection system provides value by delivering an accurate, early signal of yield-limiting events. Waiting for electrical test data after a process change instead of being able to rely on BF inspection data adds weeks of waiting time and commits more WIP to the route, making it undesirable.
To make BF inspection contribute to this yield effort, the recipe must provide sufficient capture of defects of interest (DOI) at each critical level. Recipe optimization must be tuned for DOIs while simultaneously reducing (or binning) nuisance defects, such as film thickness color variation or prior-level defects. The optimization step includes adjusting parameters such as sensitivity, illumination mode, spectral region and binning criteria of the various defect types. With many defects now too small to be optically distinguishable, an iterative approach is usually employed in which wafers (FOUPs) travel between the complementary BF inspector and SEM review tools until a satisfactory recipe is generated. However, advanced fabs require that the number of such steps be minimized to an extreme (“first-time-right”) to meet the challenging yield learning rates. We will show how a process that normally takes several weeks and involves a number of iterations is simplified and condensed into a matter of days, conforming to this goal.
The new recipe cycle optimization approach efficiently links KLA-Tencor’s BF inspection systems and SEM review tools. The method involves exchanging a data set that includes patch images and other defect-related attributes. This enables the recipe build to be completed on the SEM review tool in one iteration.
Conventional inspection recipe setup
Figure 1 shows the conventional recipe setup process flow. The goal is to find the maximum number of DOIs while minimizing the count of nuisance defects. The engineer decides on the starting pixel sizes and optics modes based on an on-tool manual check for best resolution and contrast for the current pattern level. Several promising “hot” (high sensitivity) initial BF inspection scans are performed, and the results are sent to SEM review. SEM review of hot scans can be challenging without inspection patch images to aid in defect offset and differentiate among false events — nuisance events like prior-level defects and other SEM non-visuals. If at least one sample of each DOI and nuisance type is picked up, signal-to-noise analysis will be performed on the BF inspector to determine two candidate modes to optimize.
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| 1. Recipe optimization must be tuned for defects of interest while reducing the number of nuisance defects detected. This approach takes weeks. |
Multiple BF and SEM review iterations (whose cycletime includes queue times) are required to optimize the two candidate recipes. Defect binning may be used at this point to help separate DOIs from nuisance defects. These candidate recipes are then released for comparison using production lots and sent through the production route to determine best mode and test for recipe stability and robustness. SEM review sampling for these lots follows the conventional manufacturing methodology using a limited number of randomly chosen defects for each wafer. Because feedback per wafer is limited, results from multiple lots are required to make a decision on final best mode. The conventional BF recipe setup process described above usually explores a limited number of optics modes and other BF parameters caused by time constraints. The production cycle limits the duration of this process to about four to six weeks until final release of the optimized BF recipe. Figure 2 shows the schematic overview of the conventional approach, with wafers traveling back and forth between the BF and SEM review tools.
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| 2. Schematic overview of the iterations between BF and SEM review tool in the “Conventional” setup. |
Novel inspection recipe setup
The key to the novel approach is having a SEM that can access all of the inspector’s assigned defect parameters, optical patch images, and the high-resolution optical images available during SEM review. These can help redetect defects on the review SEM, and are critical to differentiate between false defects and nuisance defects — especially prior-level, optically detectable defects. These defects are usually SEM non-visuals because the penetration depth of the SEM is significantly less than that of the optical inspector. Having superior information available on the review SEM, instead of having access to just the KLARF files (defect locations), is the key to successful recipe optimization on the SEM review tool.
The BF user interface is made available on the SEM review station in a special application. This unique integration allows the BF recipe parameters to be changed in real-time without having to rerun the BF inspection, allowing a simpler recipe setup flow (Fig. 3). The full data set from the initial BF inspection allows the user to select the best BF optics mode and adjust the BF threshold parameters offline on the review SEM, thus enabling optimized recipe settings and achieving the “first-time-right” goal. Furthermore, the binning classifiers can, and preferably should also be created on the review SEM to simplify the recipe setup process. This effectively moves the bulk of recipe optimization to a lower cost of ownership (CoO) tool, leaving more time on the BF inspector for production inspection.
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| 3. Schematic of the flow between BF and SEM review tool in the “Novel” method. A single pass is sufficient. |
Fab implementation
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| 4. SEM review image of the critical DOI: embedded contamination under the gate poly line. |
First, the conventional approach was applied to investigate a number of optics modes, pixel sizes and wavelength ranges. The threshold for the most successful recipe was iteratively adjusted to maximize DOIs while minimizing nuisance counts. Advanced defect binning was applied to bin out nuisance counts.
In the use case studied, verification of the best recipe for the conventional approach involved setting up an engineering route that allowed multiple inspections to be run on a given set of wafers. Over a six-week period, several lots were processed using the conventional manufacturing methodology. The data was then compared across the specific optics modes. The recipe determined as best resulted in the defect Pareto labeled “Conventional” in Figure 5.
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| 5. Compared with the traditionally optimized “Conventional” procedure, the “Novel with SEM” approach using the eDR-5x SEM for BF recipe optimization detected 2× the number of killer DOIs. |
At the conclusion of the conventional recipe optimization approach, the novel method was applied to the same problem: creating an inspector recipe with optimal sensitivity to the etch process defects. During this phase of the analysis, a single wafer from three different lots was used. A single inspection was run using multiple tests across the selected optics modes. This lot result then received 100% SEM review across a fixed sample plan.
Upon completing the SEM analysis, the lot was released and continued normal fab processing. The SEM results were 100% manually classified with assistance from SEM classifier software. The classified data was then used for further recipe optimization on the SEM. With the more complete data set available using this novel recipe setup approach, an optics mode different from that resulting from the “Conventional” procedure was determined to be best.
After defining the new best optics mode, further recipe optimization was performed using the SEM. First, a simple threshold adjustment was made using the Sensitivity Tuner function to minimize the nuisance defects and, second, advanced binning was used to bin the nuisance defects. The resulting defect Pareto is shown as “Novel w. SEM” recipe optimization results in Figure 5. In the “Novel w. SEM” results, counts for killer DOIs are more than double that of the “Conventional” recipe, and the nuisance rate remains very low. Moreover, all SEM analysis and derivative work was completed within a one-week period vs. the initial six weeks needed for the conventional approach.
In the case study presented, the conventional iterative recipe optimization process proved sluggish and led to compromised results. Out of the total number of defects caught, the killer DOIs category constituted a mere 5%. Choice of non-optimal optics settings was not apparent until substantial time and WIP had passed.
The novel method employing recipe optimization on the review SEM quickly revealed that the previously identified best optical mode was not, in fact, optimal at all. Using the new method, the killer DOIs count increased sixfold. Further, the fraction of killer DOI captured increased to approximately one-third of the total captured population.
Because the inspection recipe from the novel method was more sensitive to the killer DOI, optimization of the wet etch process proceeded to quickly address the killer DOI: embedded contamination. Within one week, it was possible to create an improved and verified recipe, and also address the yield-impacting defect type. This yield acceleration provided a convincing return on investment (ROI) for the new approach.
Conclusions
A novel BF recipe optimization methodology was investigated at IBM’s 323 300 mm wafer fab. This methodology demonstrated a simpler, faster and more efficient data flow, which is critical in advanced IC production. It substantially reduced BF inspection recipe optimization cycletime, enabling quicker yield learning rates and improvements in the overall equipment efficiency of the BF inspection tool. The key advantage over the conventional method lies in the SEM review system having direct access to defect and reference optical patch images from the inspector, and the ability to complete the BF recipe optimization on the SEM review station. This provides a faster turnaround and much higher confidence in the recipe. Because of the substantially increased ease of use, the novel method is much less labor-intensive and promotes significant yield savings in a wafer manufacturing fab.
Acknowledgements
Thanks to the various developers of the best-known method that enabled the presented approach, and to Chintan A. Shah for his contributions to this yield improvement effort.
