Industry News
Staff -- Semiconductor International, 4/1/2008
IBM Cuts Noise Ratio in Bilayer Graphene
Scientists at IBM's T.J. Watson Research Center (Yorktown Heights, N.Y.) have discovered that bilayers of graphene suppress noise much more effectively than single layers, leading to increased hope for graphene as a contender for post-silicon CMOS devices.
Graphene is a single layer of graphite where carbon atoms form a 2-D honeycomb lattice. With extremely high carrier mobilities and symmetry between the nFET and pFET performance, graphene is seen as "the material of the day" by the research community, said Phaedon Avouris, an IBM Fellow and group leader of the Nanometer Scale Science and Technology Group.
IBM researcher Ming-Yu Lin, who discovered the bilayer noise suppression effect late last year, said, "Graphene has very high electron and hole mobility, which makes it very appealing for electronic devices. And the electron and hole mobilities in principle are the same, all of which provides motivation for extensive efforts to study graphene worldwide."
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| IBM scientists found that bilayers of graphene have a 10× improvement in signal-to-noise ratio relative to monolayers. |
While graphene is a zero-bandgap semiconductor, researchers have learned to apply an external voltage to create a tunable bandgap of as much as ~300 MeV, sufficient for room temperature operation.
However, transistors made with a single layer of graphene suffer from external disturbances caused by impurities that scatter the carriers in the monolayer channel, Lin said. In the case of bilayer graphene, noise is reduced by a coupling between the layers, in which the two sheets form a noise suppression system by responding to each other in ways that cancel out the external disturbance.
"The interaction between the two layers gives rise to efficient noise cancellation," Lin said, with the bilayer system having a 10× reduction compared with the monolayer devices.
Noise is a major problem in nanoscale devices of any material stack, including silicon. In the atomic-scale dimensions of graphene, the signal-to-noise ratio can limit its usefulness as the noise overwhelms the signal. "As we scale down transistors, the problem is noise," Avouris said. "Noise inevitably becomes larger, and that eventually limits the usefulness of all these nanoscale devides."
"The effect of noise from Hooge's rule is exaggerated at the nanoscale because the dimensions are approaching the nearly smallest limits, down to only a handful of atoms, and the noise that is created can overwhelm the electrical signal that needs to be achieved to be useful," Avouris said.
While IBM is ultimately pursuing digital switching with carbon nanotubes (CNTs) and graphene, the zero-bandgap properties of graphene may open up early opportunities in interconnects, sensors and communications applications.
"The signal-to-noise ratio is one of most important figures of merit in terms of the smallest signal that can be detected. With reduced noise in bilayer graphene, we believe we can improve the performance and applicability of nanoscale devices. Graphene has a zero bandgap. There is no way to change that. It will always have a zero gap. That can be good for certain applications, though in logic we need a large on-off ratio," Avouris said.
Although IBM may first try to apply CNTs and graphene to analog and RF applications where the bandgap is less important, Avouris said, "We are patient, and we are in this for the long term. We may come up first with solutions for RF and analog, but that doesn't mean we are going to abandon digital. And we understand that what we do must have some advantage over what is already out there, or we are wasting our time and IBM's money."
With high carrier mobility and a desirable effective mass, graphene "makes people very excited. Now we can use it in the lab and say it is exciting. However, there are many, many technological problems before we can use it in a real-world technology," Avouris said.
Lin said the biggest challenge for graphene-based transistors is to achieve a uniform and well-controlled growth of the material over a large area. Some research groups start with a silicon carbon substrate and use very high temperatures to remove silicon atoms, leaving the carbon. This decomposition approach has shown "very promising preliminary results," Lin said.
At IBM, the research group uses the mechanical exfoliation approach, which basically involves using tape to peel off a layer of graphene that is then transferred directly onto a silicon substrate. While Lin said this approach "does not work 100% of the time, it gives us enough samples to study."
"Right now, we can make single transistors from single and bilayer nanoribbons. In the future, we need to optimize the materials and figure out the best parameters so we can show the best performance. For this device to be viable, noise is only one of the issues. Other parameters have to be optimized as well," Lin said.
— David Lammers, News EditorFreescale Forging Ahead to 45 nm in 2008
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| Lisa Su, CTO, Freescale Semiconductor Inc. |
As a member of the IBM-led Fishkill alliance since January 2007, Freescale is developing silicon on insulator (SOI) technology along with Advanced Micro Devices (AMD, Sunnyvale, Calif.) and IBM Corp. (Armonk, N.Y.)
Freescale manufactures its 90 nm SOI products at a 200 mm fab in Austin, but will move to foundries for 45 nm manufacturing starting with Chartered Semiconductor Manufacturing (Singapore). The Freescale products will use an oxynitride (non-high-k) gate oxide, she added.
"We wanted to be ahead of the curve for our networking products. When we joined the IBM alliance last year, we made the decision to jump to 45 nm as a way to best get the performance and power our customers need," Su said.
The networking products will require the technical staff to develop software that allows legacy applications to run on the multi-core networking chips.
Su said Freescale's customers tend to have long evaluation cycles, and don't move from node to node as quickly as the high-performance computer market. Networking customers "seek more capabilities, but within a given power envelope of 10 to 30 W — they are stringent about the power envelope they face," she said.
Asked if Freescale will stick with SOI technology, Su said she often faces that question. "We go through that conversation every generation at Freescale, and the answers are different and changing with time. For us, performance is important, and SOI also gives us power advantages. The resistance to soft error rates is another plus for SOI. The path to 32 nm on SOI is clear," she said.
While Chartered is Freescale's SOI foundry of record, she noted that both Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) and United Microelectronics Corp. (UMC, Hsinchu, Taiwan) have joined the SOI Consortium. While Freescale largely adheres to the Fishkill process flow for 45 nm, Su said Freescale modified its SRAM cell to adjust the threshold voltage higher and slightly thickened the gate oxide.
"Within the alliance members, we are sharing more libraries and intellectual property. That way we can all cover so much more," she said, acknowledging that Freescale's own past attempts to share intellectual property (IP) among its various product groups ran into resistance. "It is hard to share intellectual property, but it is an enabling technology that allows our design teams to spend their resources on differentiating design work," she said.
— David Lammers, News EditorIBM Brings Hitachi Into Albany Ecosystem
The 22 nm technology generation will be "an amazingly challenging node," with "challenges that people never expected to see in silicon devices," said Bernie Meyerson, vice president and chief technologist for IBM Systems and Technology Group (Armonk, N.Y.).
"As people are heading to 22 nm and beyond, we are starting to get quantization effects, band-to-band tunneling and other exotica," said Meyerson, named an IBM Fellow for his early work in silicon germanium technology development.
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| Bernie Meyerson, CTO, IBM Systems and Technology Group. |
IBM and Hitachi Ltd. (Tokyo) announced that their researchers will work together on metrology research and other semiconductor-related challenges, a move intended, in part, to aid the semiconductor equipment development efforts of Hitachi High Technologies America Inc. (Dallas). IBM and Hitachi have cooperated in exchanging systems-related products and technologies that have benefited both companies' high-end servers. Now, Hitachi will join the "ecosystem" that IBM is establishing at the Albany, N.Y.-based IBM Center for Semiconductor Research, nearby the College of Nanoscience and Engineering at the University of Albany.
Hitachi researchers will join with IBM researchers to understand the basic physics needed to produce leading-edge devices, including the metrology challenges required for characterizing 22 nm silicon.
At these advanced nodes, the industry is facing what Meyerson said are "revolutionary transitions." While the need for extreme ultraviolet (EUV) lithography is perhaps the most obvious challenge, Meyerson said all of the major manufacturing processes will undergo major changes. "The 22 nm node will be stressing every aspect of the system, including the ability to characterize the devices. In lithography, we are pushing the limits of our computational capabilities to control the optics to render that desired result."
The scope of the technical challenges requires multiple companies to pool their R&D resources, Meyerson said, leading to the Albany and Fishkill, N.Y.-based alliances formed by IBM. "Everyone brings something of value to the table. All share and make use of the results," he said.
For Hitachi, which has placed its logic manufacturing into the Renesas Technology Corp. (Tokyo) joint venture with Mitsubishi Electric Corp. (Tokyo), the relationship with IBM will benefit its central research laboratory and the various systems businesses of Hitachi. On a more immediate level, it will give the Hitachi metrology and semiconductor equipment operations entry to IBM's research efforts.
"This effort will focus on the latest technology to analyze devices and structures, and the metrology to do that analysis. We are both working to identify the limits of technology, and then to understand the critical issues around device physics. Hitachi has become another member of the center for semiconductor research at Albany, another member of the ecosystem," Meyerson said.
— David Lammers, News EditorLuAG, Other High-Index Immersion Elements Get Boost
Although most chipmakers will use immersion lithography at the 45 nm node, it's unclear what the best option will be at 32 nm. One option being considered as a possible extension of water-based immersion is immersion lithography using high-index materials. Until recently, however, the prospects for really making a go of it were dim.
The mood changed last month at the SPIE Advanced Lithography conference, where progress was reported on Generation 2 immersion fluids (with a refractive index of ~1.65) and their associated recycling and lens contamination issues, and most significantly news came from Schott Lithotec (Jena, Germany) on its impressive progress on lutetium aluminum garnet (LuAG) materials for high-index lens elements.
Lutz Parthier, who is responsible for the LuAG project and head of development at Schott Lithotec, said researchers have achieved an absorption of 0.05 cm-1 — a significant improvement over the 0.11 cm-1 that Parthier reported at the Immersion Symposium in Keystone, Colo., last fall. And although there is still more progress to be made to reach the final goal of 0.005 cm-1, the latest level was the requirement set by the exposure tool manufacturers for them to feel comfortable pursuing high-index immersion tools.
The impetus behind such tools is that higher-index materials will enable higher numerical apertures (NAs) in the exposure lens, effectively reducing resolution. Patterning at the 45 nm node will make use of water-based immersion tools with NAs as high as 1.35. The use of a Generation 2 immersion fluid, however, would enable an NA of up to 1.45, and incorporating a high-index lens such as LuAG would boost NA further to 1.55. The ultimate goal is NA=1.70, which would require a Generation 3 immersion fluid with an index of refraction of ~1.8, as well as similarly high-index photoresists.
Peter Krüll, Schott Lithotec's vice president, called high-index immersion lithography the perfect technology to prolong immersion. Inserting extreme ultraviolet (EUV) lithography even at the 22 nm node looks questionable, he said, and it still faces several potential showstoppers. Meanwhile, double patterning, another option for extending water-based immersion lithography, is an expensive alternative.
Although there are certainly risks associated with the development of the high-index lens materials, Krüll said, Schott's experience with CaF2 (which would've been needed in larger quantities and at higher quality levels for 157 nm lithography) has helped them be more prepared to LuAG development. For example, intrinsic birefringence was a completely unknown problem that came up suddenly with 157, but has been a known entity for LuAG. Schott researchers are doing their homework, he said, and they are pushing the team hard to get it done. By around the end of March or beginning of April, Schott plans to make LuAG materials available to anybody who wants them, Krüll said, to help them in further development work.
Other teams are continuing work on high-index immersion as well, tackling various issues surrounding the materials. High-index immersion presentations were also given by toolmakers Nikon and ASML, immersion fluid suppliers JSR and DuPont, and MIT's Lincoln Labs. JSR and DuPont have both made good progress in Generation 2 (n~1.65) immersion fluids, improving their understanding of and solutions for transmittance change, lens contamination and recycling.
Of considerable concern has been lens photocontamination, but progress has been made on understanding and mediating contamination, and there are now at least a couple promising methods for cleaning the optics. Vlad Liberman presented the work that has been done at Lincoln Labs, showing that the optics could be cleaned with a very minimal amount of hydrogen peroxide.
ASML's Harry Sewell highlighted several areas in his presentation, including various concepts for improved fluid delivery and a different scheme for cleaning the optics as they become contaminated. Nikon's Hiroyuki Nagasaka detailed work his company has been doing on optimizing the final lens processing for the LuAG material, showing promising results on polishing's ability to bring birefringence closer in line with fused silica.
There has also been concern about scan speed capabilities with high-index fluids, which exhibited problems when put into water-type flow systems. But the toolmakers have been working on new flow candidates, and are no longer concerned. In fact, Canon presented a poster showing that they have been able to achieve 800 mm/sec scan speeds with high-index immersion fluids.
— Aaron Hand, Executive Editor, Electronic MediaKyosemi Uses Ball Diodes in PV Modules
At the Second International Photovoltaic Power Generation Expo in Tokyo, Kyosemi Corp. (Kyoto, Japan) demonstrated a transparent photovoltaic (PV) cell made of an array of hundreds of small ball p-type/intrinsic/n-type (PIN) diodes, which deliver high efficiency.
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| Kyosemi Corp. creates solar PIN diodes by dripping molten silicon in a gravity-less environment to form round silicon balls. |
A single PV cell shows a relatively high efficiency of 17% when positioned on a piece of reflective white paper, comparable with that of conventional silicon crystal solar cells. The ball diode easily absorbs light globally and reaches the 17% rate because light reflected to the backside can be processed. Efficiency is higher than amorphous silicon PV cells, according to the company.
The spherical silicon crystals are made in a gravity-less environment. In a furnace, molten silicon is dripped from a height of 14 m, and surface tension causes multiple drops to form. Under space-like gravity for 1.5 sec, crystallization occurs naturally. Several thousand crystalline spheres form each second and are then cooled. The solid balls roll out from the bottom of the chamber.
Kyosemi produced six different modules as engineering samples, with the diodes arranged 12 in series, 2-parallel/6-series, 3-parallel/4-series, 4-parallel/3-series, 6-parallel/2-series and 12-parallel connections. The engineering samples are presently shipping.
The diodes have an open voltage of 0.6 V, a current of 2.5 mA and output power of 1.5 mW. The module characteristics are based on 1.2 V and 15 mA specifications for the 6-parallel/2-series module, for example.
— Kenji Tsuda, Asia Contributing Editor
