Practical Ways to Lower Probe Costs

The cost of test at wafer probe usually focuses on the obvious cost of the probe card and its non-recurring engineering (NRE) charges, but this article highlights other first-order parameters that can dramatically lower the cost of test at wafer probe. Using the probe card cost of ownership (CoO) model developed by the International Sematech Manufacturing Initiative (ISMI, Austin, Texas), presented here are real-world scenarios covering high- and low-volume system-on-a-chip (SoC) test. We conclude with anticipated per-die cost savings, and offer guidance on how to substantially lower test cost at probe.

Increasing pin count

Over the past several years, the price of probe cards has escalated because of several factors. These include increased complexity, finer pitch, higher performance and, most importantly, significantly higher pin counts. The result is that the average spending on the procurement of a new probe card has risen from a few thousand dollars a decade ago to multiple tens of thousands of dollars for today's cards that test state-of-the-art logic and memory wafers.

Parallel test on memory devices has increased to the point where most DRAM devices are tested with cards that touch down on all devices simultaneously across whole wafers up to 300 mm in diameter. Parallel testing of flash memories has also increased. Both of these have resulted in memory probe cards with a very large number of probes spanning entire wafer surfaces. Logic probe cards have seen pin counts escalate because of testing larger, more complex chips with more I/O pins, multi-core internal parallelism, limited parallel test and, most significantly, more power and ground pins to handle the heavy power distribution while minimizing electrical noise. Because probe card cost is primarily a function of pin count, the price of these cards is increasing.

Modeling probe card CoO

However, the probe card and its NRE expense are not the only costs involved when probing ICs. The Probe Council at ISMI has developed an excellent Probe Card Cost of Ownership Model,¹ which takes into account the various factors that impact the cost of probing. These include yield, volume, factory loading, test time, index time, setup time, probe cleaning, probe card lifetime (number of touchdowns), maintenance and repair. Performing sensitivity analyses on the model, one can see that discounting the price of a probe card by 20% only results in an ~11% reduction in the actual cost of testing a die at wafer level. However, doubling the lifetime of a probe card can, in itself, lower the test cost per die at probe by almost 20%. Improving maintainability of the card to enable fast on-site repairs by the customer instead of factory repairs by the card vendor can reduce the test cost per die at probe by a further 30%. These are, in fact, the first-order impacts on the cost of test at wafer probe. Let's look further into each of these.

Probe card lifetime is typically a function of the combination of normal wear and physical or electrical (burned probe) damage. Wear mostly occurs during the process of online probe card cleaning, when mildly abrasive pads are used to clean off the accumulated oxides and contamination that naturally occur in the probing process. Online cleaning is programmed to take place automatically on the wafer prober after a pre-selected number of touchdowns have been made. The online cleaning frequency is set to occur just before the probe contact resistance rises to the level where it might negatively impact yield. Probes made with harder materials will wear slower during the cleaning process, and probes with inherently better contact resistance will require less cleaning.

Probe damage can be caused by either a simple mechanical accident or excess current being channeled through a single probe, which can result in a burnt tip. With most of today's advanced probe card technologies, whether it be vertical-, membrane- or MEMS-based technologies, the repair of damaged probes usually requires that the probe card be sent back to the original manufacturer. This necessitates an expensive and time-consuming refurbishment process, which also requires that additional spare cards be carried in inventory to prevent downtime while the repair is made.

Applying the model

In the following scenario, we compare the performance of a Wentworth Laboratories' Accumax probe card, a typical Cobra probe card and a typical MEMS-based probe card. The proprietary probes used in the Accumax offer high current-carrying capability to minimize the potential for the probe tips to be burned. They also have hardness characteristics that minimize wear during cleaning cycles. Users have found that their in-house technicians can effectively replace damaged probes on-site in under 15 minutes, obviating the need to return the card to the supplier's factory for repair.

We set all other parameters, such as pricing, test time, yield, etc., to have equal values for each scenario and inserted only the differences shown in the Table. These values are based on actual user experiences. Figure 1 shows the model output for a high-volume SoC device running a total of 12 million devices over a period of just over two years. The result is a $1.8M savings over the life of the product, with a 50% lower cost of test at probe shown by the $0.16 per-die test cost on Accumax vs. $0.32 per-die test cost for the MEMS-based scenario.

1. Over the lifetime of the product, $1.8M can be saved by using the Accumax probe cards (scenario C) vs. the MEMS-based cards (scenario A); per-die test cost savings is $0.16/die vs. $0.32/die, respectively.

Because not all SoC products run to such high volumes, we modeled a lower-volume scenario of two million devices over a two-year lifetime (Fig. 2). As one would expect, until one million chips have been tested, there is no difference in test cost per die. However, with over one million units, the cost quickly starts dropping and by two million, the savings comes in at 35% as evidenced by the $0.18 per-die test cost on Accumax vs. $0.28 per-die test cost for the MEMS-based scenario.

2. At lower volumes, per-die test-cost difference is not realized until volumes exceed one million good die, but at 1.2 million and beyond, both the total cost savings and per-die test-cost differences are evident.

Another way to look at the model output is to look at the total cost of probing over the lifetime of the product. The results of this for the above high-volume scenario can be seen in Figure 3, which shows that extended lifetimes and lower maintenance costs can reduce the actual probe card-related costs from dominating the total test cost to becoming a fraction of the test time or automated test equipment (ATE)-dependant costs.

3. With previous-version probe card technologies, the probe card cost tends to dominate overall test cost. The extended lifetimes and lower maintenance costs associated with the Accumax probe card translate to lower total cost of test and less probe card contribution to test costs.

As they say in the auto trade, "Your mileage may vary," but the ISMI model clearly validates our assumptions that the best way to substantially lower the test cost at probe is to place a heavy emphasis on procuring probe cards with long lifetime and field maintainability, then focus on fine-tuning the wafer probing process for optimum results.