Solid-Source Delivery System Enables Hafnium-Based Gate Dielectrics

With every successive technology node, geometry scaling has provided the means to improve CMOS device performance with minimal changes to conventional manufacturing process flows. The transistor gate dielectric, one of the most critical layers in the entire IC architecture, has been SiO₂-based since the invention of the solid-state transistor in 1947. The gate dielectric functions to insulate the transistor channel from the gate electrode, and its equivalent oxide thickness (EOT) is characterized by an inverse relation to the material's k value. CMOS scaling has led to the aggressive thinning of EOT, resulting in marked performance improvements, albeit with large increases in leakage currents. Still, the industry has successfully scaled SiO₂-based gate dielectrics for more than 50 years, down to a thickness of only several atoms. In recent years, this has been accomplished by increasing the film's k value with the controlled addition of nitrogen to form SiON. Using higher-k films enables continued scaling of EOTs, using thicker films to reduce electrical leakage.

ASM’s Pulsar 3000 ALD reactor process chamber enables volume manufacturing of high-k dielectrics for leading-edge CMOS and non-volatile memory process flows with high-quality film and composition uniformity.

Deposition challenges

The integration of these new materials into the CMOS process flow is not straightforward. Hafnium-based materials must be deposited instead of grown from the underlying silicon substrate. However, because the gate dielectric is the transistor's core, deposition techniques must now approach the thickness uniformity and defect performance of thermal furnaces to maximize device yield. Furthermore, the deposition of these materials must be tightly controlled because minor variations can lead to EOT thickening or threshold voltage (V_t) shifts caused by work function modification from fixed charges, dipole moments and thermal treatment.

Hafnium oxide can be deposited by physical vapor deposition (PVD), metal organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD). PVD has been largely ruled out for this application because of concerns with surface damage and thickness/interface control. MOCVD has the advantage of higher deposition rates, but the inherent higher deposition temperatures needed for this technique pose risks of interfacial layer thickening, which brings into question the potential for future scaling of the new dielectric material. Thickness and uniformity control is also very difficult in the ultrathin deposition regimes. ALD has emerged as the leading candidate for high-k gate dielectric deposition because it uses a series of self-limiting surface reactions to precisely grow the film monolayer by monolayer, with minimal impurity levels, low surface roughness and ultimate thickness control. ALD is a low-temperature deposition process (typically <400°C) with weak temperature dependence. This allows for process robustness, as the deposition window is usually large and stable. The superior deposition conformality inherent to ALD also makes it a natural choice for gate-last and finFET devices.

Precursor choices

Lower deposition temperature techniques allow lower oxidizer activity but, in turn, require higher reactivity of the precursor toward forming a highly pure, extremely uniform thin oxide film. Another set of challenges stem from the precursor sources' nature. Metalorganic sources with suitable vapor pressure for CVD and ALD exist. Some of these are liquids, allowing for a liquid delivery approach, while others are solids (which also may be injected via liquid delivery when dissolved in suitable solvents). Early CVD efforts demonstrated composition control of (Hf,Si)O₂ films and relatively low carbon levels using both oxygen- and non-oxygen-containing metalorganic sources with deposition rates in the range of 60 Å/min at 590°C and 15 Å/min at 550°C, respectively.^3,4 Several end users have confirmed that the most promising metalorganic sources for hafnium-oxide deposition is the family of metal amides tetrakis(ethylmethylamido) hafnium (TEMAH), tetrakis(dimethylamido) hafnium (TDMAH), etc.⁵ However, it is still debatable whether these sources can be used to deposit films of the purity needed for the extremely demanding gate dielectric application. A remaining key question is whether carbon levels can be low enough while balancing the oxidizer activity with the possibility of transistor channel degradation.⁶ Furthermore, metal amide-based precursors (e.g., TEMAH) decompose above a critical temperature, leading to increased impurity content and decreased film density at higher deposition temperatures. This limits the temperature for ALD growth and delivery of precursor to the reactor.

1. The data was collected on n-channel transistor devices with TaN electrodes. Use of an optimized chemical interface shifts the leakage trend line, allowing sub-nm EOTs. (Source: ASM, IMEC)

The use of halide-based sources for hafnium — in particular, HfCl₄ — avoids the carbon issue. Halide precursors are thermally stable and do not show decomposition effects. Although there have been concerns with residual chlorine impurities with the use of HfCl₄, proper deposition techniques can reduce chlorine levels in the gate dielectric to much less than 1%. Furthermore, it has been demonstrated that the level of chlorine impurity has no effect on bias-temperature instability (BTI) reliability.⁷ HfCl₄ deposition also uses water as an oxidizer, resulting in a process that is very gentle to the interface, which is imperative to further enable dielectric thickness scaling. With proper interface control, EOTs as low as 0.75 nm have been demonstrated for high-performance devices.⁸ Figure 1 shows the electrical advantages of HfCl₄ over TEMAH in a high-thermal-budget process flow. The HfCl₄-based process shows almost two orders of magnitude reduction in leakage over the TEMAH-based process and demonstrates excellent scaling results to EOT below 0.8 nm. Figure 2 also shows that HfCl₄-based films demonstrate higher transconductance compared with TEMAH-based films. The primary challenge to using HfCl₄ is the very low volatility of the precursor (~0.3 Torr at 150°C). A novel delivery system overcomes this obstacle.

2. Metalorganic-based films may introduce carbon contamination to the transistor channel and degrade carrier mobility, resulting in lower peak transconductance.9 (Source: Freescale Semiconductor)

Delivery fundamentals

The most obvious issue in using a low-volatility precursor is the need for the source to operate at higher temperatures, creating a need for valves and seals that are able to reliably operate at these elevated temperatures for long periods of time. However, the delivery of a solid precursor has other unique demands. The key to stable and repeatable delivery of a vaporized solid in a carrier gas stream is to control the solid/vapor interaction.

Multiple factors have a significant impact on the equilibrium between the solid and gas phase. Perhaps the most important of these is the nature of the solid material itself. The particle size of the solid, as well as its crystalline phase (and degree of crystallinity), will affect the amount of surface area exposed to the gas interface for a given area of exposed solid. Moreover, this exposed surface area will change as the solid precursor is delivered. Of course, simple depletion of the source will change the surface area, but the surface effects during sublimation can also alter the surface morphology, which can increase or decrease the relative surface area depending on the conditions and the percentage of time that the material is held in a static equilibrium state. To optimize the saturation of the gas stream, the effects of surface morphology and exposed surface area must be mitigated. Also, thermal equilibration throughout the source material must be carefully controlled to maintain the gas phase's equilibrium saturation. Proper temperature control will also prevent material condensation that can clog the source flow or otherwise disrupt the source ampoule's normal function.

3. Innovative vessel design ensures that carrier gas is saturated with precursor when delivered to the deposition chamber. Precursor utilization is very high, leading to lower process cost of ownership. (Source: ATMI)

The design also provides for a convoluted gas flow path, with the gas inlet stream initially delivered into the ampoule's bottom and flowing sequentially through each tray as it migrates toward the outlet of the ampoule. These design features optimize the contact of the carrier gas with the exposed surface of the solid source. This mitigates the effects of changes to the solid surface area because of material depletion and surface morphology changes during delivery. The heat transfer characteristics of the ampoule and carrier gas stream's intimate contact provide a highly repeatable level of saturation, whether used in pulsed or continuous delivery modes.

4. Proper solid-source delivery design is imperative to meeting high-volume manufacturing requirements. This source is capable of continuous operation at temperatures as high as 250°C. (Source: ASM)

CMOS manufacturing with solid sources

Volume production of hafnium-based gate dielectrics has begun to ramp in the past year. Contrary to many skeptics, it has been proven that solid-source precursors such as HfCl₄ and ZrCl₄ are manufacture-worthy and not limiting factors to attaining the rigorous production specifications for leading technology nodes. High-k gate dielectric production requires exceptional within-wafer uniformities and tight control of wafer-to-wafer and lot-to-lot uniformities. Figure 5 shows volume marathon data of more than 3000 wafers run on an ALD process module with a HfCl₄/H₂O system on a single reactor pack without maintenance intervals or reactor cleans. Cross-lot uniformities are below the limits of thickness metrology capabilities, and overall wafer-to-wafer uniformities are below 0.5%. Within-wafer thickness ranges of <1 Å can be achieved. Moreover, particle performance is extraordinary — typically demonstrating single-digit adders at a 0.10 μm threshold size.

5. Insertion of high-k gate oxide deposition into a manufacturing process flow requires extensive film stability data and demonstration of defect performance rivaling thermal oxidation processes. (Source: ASM)

Cost of ownership (CoO) is an important factor in the manufacturing of any process. Deposition of hafnium oxide from HfCl₄ has the added advantage of being the lowest cost solution, with the precursor cost running <50% of MOCVD liquid precursors. Additionally, precursor shelf life at temperature is vastly superior because decomposition is not an issue. Coupled with the low consumption rate of the precursor for ALD applications (<1 mg/ALD cycle) and extremely thin deposition layers (<20 Å), a 500 g fill of precursor, packaged in a highly efficient vaporizer, can be expected to last in excess of six months in a production environment for gate dielectric applications. Novel vessel and delivery designs enable repeatable and stable chemical dose delivery to the ALD reactor. To monitor vessel stability over time, a wafer in a cross-flow ALD reactor can be intentionally underdosed and the film deposition front can be inspected. Figure 6 shows results from dosing profile checks throughout the life of a single solid-source vessel. The pulse front does not move significantly over deposition of 11,000 wafers, showing the extreme stability and repeatability of the vessel and solid delivery system.

6. Using a cross-flow reactor, precursor dose variation can be monitored by inspection of the film front on an underdosed wafer. There is no significant change in film profile over 11,000 wafers run on a single solid-source vessel — showing innate dose reproducibility of the vessel and delivery system. (Source: ASM)

Tools in volume production must minimize downtime because of invasive maintenance and subsequent process start-up tuning. When properly designed, solid-source delivery systems can provide world-class equipment dependent uptimes. Figure 7 shows the wafer-by-wafer response of an ALD toolset to vessel replacement/refill and reactor clean/replacement — two of the most invasive maintenance procedures during normal operation. Mean thickness and particle performance are unaffected by maintenance procedures, and no process tuning is required prior to the processing of production lots. This data highlights the inherent stability of a well-characterized vessel and delivery system. Another requirement of production toolsets is the ability to fingerprint and match processes from site to site. Figure 8 shows the thickness stability (at initial start-up) observed across a fleet of tools over several sites. Mean variation is below metrology limits, even though the tools use discrete solid-source vessels and reactor packs and have variations in facilities implementation.

7. Mean variation and defect performance are not affected by invasive maintenance when delivery systems are designed well. Wafer-by-wafer recovery after a reactor and solid source vessel change is shown here. Dummy wafers and lengthy temperature tuning runs are not required. (Source: ASM)

The high-k/metal gate revolution has arrived, requiring the adoption of new process technologies and the development of precursors and delivery techniques to enable volume production of hafnium-based gate dielectrics. ALD using novel solid-source delivery has facilitated the move to new gate materials while maintaining the potential to scale transistor geometry for future nodes. Demonstration of production-worthiness of these new techniques has required, and will continue to require, good synergy between material suppliers and equipment manufacturers. Together, these strategic partners can ensure that device manufacturers have all the options available to them to continue to advance transistor technology well into the 21st century.

8. Process matching across worldwide fab locations is essential to device manufacturers. Here, a sample of a fleet of ALD modules demonstrates minimal variation in deposited high-k film thickness, ensuring that device performance can be matched irrespective of manufacturing facility location. (Source: ASM)