Software Giants and Startups Tackle Lithography Complexity
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 3/12/2008 11:30:00 PM
Every year at the SPIE Advanced Lithography conference, the EDA sector seems to gain a little more prominence. While the bulk of the presentations, particularly looking to the next generations, still focus on tackling hardware and materials issues, there is no question that the software is enabling so much of the present-day advances keeping the industry on track.
This year’s conference, which took place again a couple weeks ago in San Jose, featured several announcements from the key players in the EDA space — such as Mentor Graphics, Synopsys, Cadence, Brion Technologies, Luminescent — and also carried the buzz about a couple of the latest newcomers, including Gauda and Tela Innovations. Much of the focus was on getting all the incredible amounts of data that are the necessary outcome of increasingly complex masks through the pipeline. Of course there was much talk about double patterning, and what the software providers are doing to solve key design splitting issues, but there was also talk about how they could help chipmakers avoid double patterning for just a little while longer.
Understandably, a great deal of buzz centered around the eventuality of relying on double patterning techniques to bridge the gap between water-based immersion lithography and extreme ultraviolet (EUV) lithography. While there are such issues as overlay requirements that fall into the purview of the toolmakers, there was much to be said from the EDA folks about how the design layers would be split into their respective masks.
Brion Technologies, for example, came out with its announcement the first day of the conference regarding two products — particularly its Tachyon DPT — that are better equipped to deal with computational lithography as it relates to double patterning.
Although Cadence did not officially announce news at the show, the company has been busily integrating capabilities from recent acquisitions such as ClearShape and Invarium into its own Virtuoso products to create a unified front-to-back design environment. With the spotlight on double patterning, Cadence recognizes the importance of an integrated approach to deal with complex issues such as split problems and conflicts, and overlay variation.
Their outlook is that they are starting with a “clean sheet” on the integration of these products, with no previous generations to bog them down. What they’re aiming to do is to incorporate new effects into the tools in a way that is transparent for the users, while also being flexible enough to support whichever double patterning techniques ultimately take hold in the marketplace.
Speeding things up
Any move to double patterning is only going to intensify what is already an overloaded industry in terms of mask complexity and its ensuing data file sizes, which are reportedly nearing terabyte sizes.
One new startup, Gauda Inc., came out at SPIE with a demonstration of its technology that it says accelerates OPC up to 200× faster than traditional solutions while running on desktop computers. It does so through new algorithms using CPUs and GPUs traditionally used for gaming.
Gauda isn’t the only one taking advantage of technology creating for gaming in the effort to break through the data bottlenecks resulting from today’s complex mask designs. Mentor Graphics, IBM and Mercury Computer Systems have teamed up to see if stringing a bunch of PlayStation 3 systems might get the job done — well, kind of. Mentor Graphics has been accelerating its Calibre nmOPC and OPCverify computational lithography tools with IBM’s Cell Broadband Engine processor technology, which was originally developed for the PS3. According to Jim McKibben, director of market development, advanced computing solutions, at Mercury, which optimized the Calibre tools for the Cell processor, Mercury got together with IBM to see if the Cell might make sense for parallel computing.
The previous manifestations of Calibre were not designed for parallelizable operations, McKibben said, so it started taking too long. It might take a couple days, for example, to run OPC on a critical metal layer. So if an operator got a couple false positives, he would crank up the system and start ignoring the flags, he said.
Now Mentor’s Calibre has been qualified for production at IBM for 45 nm and smaller process nodes. With test cases on a 45 nm core, IBM has experienced a 3-4× speedup in computation time, according to Tim Farrell, distinguished engineer at IBM Microelectronics. Put another way, for a comparable run time, the investment in IT is less than the conventional approach – 75% or as low as 60% of the previous investment, depending on the scale of the approach, he said.
The idea of throwing thousands of standard processors at the problem, as some other providers do, is not an idea that is appealing to the customer, according to Joe Sawicki, general manager, Design-to-Silicon Division, at Mentor Graphics. Instead, Mentor’s solution takes a base of standard X86 processors, and accelerates by throwing a few Cell processors into the mix, which are better suited for offloading selective complex functions.
The reduction in the cost of ownership and also the faster turnaround time allows IBM to mitigate the increase in complexity at the 45 nm node, according to Farrell.
Synopsys, however, has a somewhat different view on the potential solutions, introducing during SPIE its Proteus Pipeline Technology, which has the capability to pipeline key manufacturing applications, thereby reducing the time needed for operations and eliminating the bottleneck in what is approaching terabyte-sized data files.
From Synopsys’s viewpoint, it’s better to focus on a software-based approach and leave the hardware optimization to companies like Intel. At the Photomask conference last fall, Synopsys announced that it was moving to a quad-core approach, based on a close relationship with Intel, according to Tracy Weed, director of the manufacturing products group at Synopsys, who added that that was far superior to any hardware acceleration approach. “I haven’t seen anything that can beat Intel’s roadmap,” he said.
In traditional serial manufacturing flows, a complete post-OPC database must be available before applications later in the process can be initiated. With Synopsys’s pipelining concept, applications such as resolution enhancements techniques (RETs), OPC, mask rule checking (MRC), lithography rule checking (LRC), mask data preparation (MDP) and user-customized geometry operations are run concurrently. As Weed noted, this effectively brings MDP to a zero runtime.
Please, no double stuff
As much as double patterning is recognized as a potential solution, most chipmakers would like nothing better than to never have anything to do with it in their production processes — with its increased cost, complexity and hit in production throughput. Will Conley of Freescale, for example, mentioned in passing how his company was having to really reevaluate its chip designs to make them more litho-friendly — anything to avoid costly double patterning schemes.
Inverse lithography, a term introduced by Luminescent at the 2005 Photomask Technology conference, has become more of a household phrase, and Luminescent is no longer the only company throwing the idea around. Logic companies are particularly interested in the concepts behind inverse lithography, according to Kurt Ronse, director of lithography at IMEC. Advanced imaging solutions such as EUV lithography and double patterning can have enormous impacts on costs for logic manufacturers, he said, so relaxing pitches here and there is a preferable solution.
In its efforts to steer clear of double patterning for as long as possible, Texas Instruments is exploring more realistic layouts, and really taking a close look at such things as forbidden pitches for its contacts, according to Jim Blatchford, manager of lithography development at TI. As they try to assess what the performance of those holes will be in a real layout, however, they’re finding that “a great fraction of the holes that are forbidden are actually OK,” Blatchford said.
TI, whose Steven Prins presented a paper at SPIE about using inverse lithography as a DFM tool, is continuing its long tradition of restrictive design rules, according to Blatchford. As Prins explained in his presentation, getting any analysis done requires an awful lot of work, which all has to be redone any time illumination conditions are changed, for example. So TI is using Luminescent’s Litho Explorer (LE) to automatically generate the theoretically optimum OPC and SRAF treatment for each layout, and for each potential illumination scheme. “Ideal” masks are generated to explore physical limits, then “Manhattanized” to make them more realistically manufacturable. This approach has enabled TI to explore several thousand illumination conditions.
TI’s application opens up a whole new application area for Luminescent’s inverse lithography, according to Leo Pang, general manager of lithography products at Luminescent. The company has been able to explore its use as a DFM tool, trying to capture simulation models and incorporating OPC and SRAFs into the model.
Also at SPIE, one company debuting a concept to help keep double patterning at arm’s length was Tela Innovations, with its vision for on-grid, straight-line, one-dimensional layout structures. According to Neal Carney, vice president of marketing at Tela Innovations, rethinking designs and regularizing layouts is exactly the sort of the thinking that is enabling Intel to produce its Penryn at the 45 nm node with dry lithography. It uses a very regular layout structure, with fixed topologies and fixed spacing, he noted. (As a side note of interest, also announced during SPIE was that Intel Capital invested in Tela Innovations during its Series B round of funding.)
Tela’s solution uses pre-defined physical topologies that enable a lithography-optimized layout that is a more one-dimensional approach to design. It avoids corners, which are difficult to resolve and are disruptive for adjacent shapes, and also shies away from irregular pitches. The approach instead puts everything on a grid, including vias, which are typically scattered everywhere, according to Carney. If they’re on a grid, he noted, it’s also easier to add OPC to them.
And Tela has figured out how to create the one-dimensional structures in an efficient way, Carney said, to actually reduce the area 10-15% for logic designs. In the past, attempts at 1-D structures have had to sacrifice footprint, typically running larger than their 2-D counterparts. The approach also enables a 2.5× reduction in leakage, Carney added.
Tela presented its concepts at SPIE in a paper with Brion regarding low-k1 logic designs at 32 nm, and a poster with Applied Materials on pitch halving for 22 nm logic cells.
While the importance of computational lithography continues to grow in this space, we will see companies coming and going, and the big EDA companies trying to tackle the problems with new solutions. The fact is, in this era of deep sub-wavelength imaging, they are shouldering much of the burden for keeping the industry on Moore’s Law. And the industry needs some innovative ideas to keep it going.
