ITRS Yield Enhancement: The End Justifies The Means
Laura Peters, Lead Technical Editor -- Semiconductor International, 3/12/2008
The 2007 Update of the Yield Enhancement chapter of the International Technology Roadmap for Semiconductors (ITRS) was recently released, and it defines the difficult challenges in the short term (≥22 nm) and long term (<22 nm), with the approximate defect budgets needed to obtain acceptable yields on semiconductor devices at those nodes. With yield improvement, it is fair to say that the end justifies the means: High early yields and fast yield ramps do justify an aggressive yield enhancement strategy, and will hopefully translate to future optimized control limits, sampling strategies and defect sourcing methods.
As was the case of the last major update to the roadmap in 2005, the No. 1 challenge with yield enhancement is the ability to detect defects of sizes that scale as quickly or faster than the device features, which requires greater sensitivity of measurement — something that traditionally has gone hand-in-hand with lower-throughput tools.1 The need for higher sensitivity (signal: noise) increases the defect counts while, at the same time, it is a challenge to separate false or nuisance defects from killer defects. All of this is accompanied by a need to keep inline inspection costs low.
Because the cost of tools, fab space and throughput of defect detection tools most influence cost of ownership (CoO), fabs tend to deploy inspection tools in a sparse sampling mode. The yield enhancement international technology working group (ITWG) suggests that to maintain acceptable CoO in the future, throughput, sensitivity and the use of adaptive recipe options on the tools must be increased. Better understanding of non-visual defects is needed (defects causing electrical failure with no physical footprint), and macro defects should not be ignored in the rush to better identify micro defects.
Die yield is the product of material defect-limited yield, random defect-limited yield and systematic mechanism-limited yield (SMLY); assumptions are made for each device type (Table). In the ITRS yield model, Yrandom is calculated using a negative binomial model, but a general formula for Ysystematic or SMLY is unknown. With each device generation, SMLY loss has an increasing impact on yield ramp rates and attainable yield levels. Better methodologies are needed to understand, model and eliminate sources of SMLY loss. For instance, yield modeling assisted by CAD or SMLY model-based design for manufacturing (DFM) research is required. One approach would devise test structures to classify and quantify SMLY and/or non-visual defects.
All the defect budget targets in the roadmap are based on a survey of Sematech (Austin, Texas) member companies that was carried out seven or more years ago (1997, 1999 and 2000). In 2005, the yield enhancement ITWG suggested an update of this database (containing particle per wafer pass [PWP] levels from 164 tools, 30 tool types) be performed, but it was not carried out in time for the 2007 Update. Nonetheless, the yield model and defect budgets provide one benchmark for the industry to follow for the maximum allowable levels of random PWP by tool type for the ≥34 nm critical defect size (for microprocessors) and ≥40 nm critical defect size (for DRAM/flash).
Yield learning requires rapid identification of defect and fault sources through integrated data management (IDM). For IDM, improved algorithms are continually needed for yield impact assessment, automatic defect classification (ADC), spatial signature analysis (SSA), adaptive sampling and more rapid decision-making.
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2005 was the first year that wafer edge and bevel yield loss were identified as critical elements in overall yield loss. Appropriate defect inspection methodologies are being developed for the front and backside wafer edge. Backside inspection must preclude contact or contamination of the wafer frontside. Likewise, more effective tools are needed to probe high-aspect-ratio (>3:1) contacts and vias, because electron-beam (e-beam) tools do not meet the needs of high throughput and low cost. There is a need for greater sharing of tool defect data between semiconductor manufacturers and equipment manufacturers to specify design processes and the required equipment. Presently, there are no known solutions for detecting smaller defects at higher throughput, measuring CDs at higher throughput, and controlling wafer flatness of patterned wafers.
Another issue that has been highlighted in previous roadmaps is the need to correlate process fluid contamination types and levels to yield to determine control limits. Impurity concentration needs to be correlated with device yield, reliability and performance. In the absence of such correlations, the yield enhancement ITWG does not call for order-of-magnitude improvements in purity of gases or liquids. Instead, it calls for innovative ideas for removing contaminants from reusuable process gases or fluids, with a focus on the point of process (the wafer environment). In the case of recycled media, such as ultrapure water, improvements are needed in rapid online analytical technology, especially detection of organics, to ensure point-of-use quality of recycled water is the same or better than that of single-pass water.
Future needs
The 2007 ITRS calls for an update to the PWP data mentioned, which may include some additional tools or tool types.
To improve optical defect detection systems, the move is toward shorter wavelengths; continuous wave lasers; detectors with higher quantum efficiency and higher acquisition speed; suitable low loss, low aberration lenses, waveplates and polarizers; and robust mechanical and acousto-optical scanners. For e-beam inspection, speed improvements are needed, as well as the ability to filter out defects of interest.
Equipment defect targets have traditionally been based on horizontal scaling. Vertical faults, particularly as they apply to the gate stack, metallic and non-visual contaminants and parametric sensitivities need to be better understood.
When new materials are being developed, such as high-k dielectrics, it is important to collect and report environmental and material purity data so that later yield enhancement efforts can proceed with some technical basis.
At the wafer level, affordable, accurate and repeatable real-time sensors for non-particulate contamination are becoming increasingly necessary. Storage and transport environments are becoming more critical to the process. For instance, pre-gate and pre-contact clean, salicidation, exposed copper and reticles are requiring inert environments, and increased use of inert environments may be dictated in the future.
- L. Peters, "2005 ITRS: Analyzing Smaller Defects Faster," January 2006, Vol. 29, No. 1.
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