Thermal Copper Pillar Bumps for Thermal, Power Management
A new approach to electronic thermal management uses thermal copper pillar bumps to provide appropriate cooling where and when it is needed within the electronics system.
Phil Deane, Nextreme Inc., Durham, N.C. -- Semiconductor International, 3/1/2008
Active cooling of any device is most efficient when it occurs closest to the source of heat generation. All advanced central processing units (CPUs) and graphics processing units (GPUs) today are packaged in a flip-chip format, where solder bumps are placed directly over the active area of the die. A new approach integrates a thermally active material into these solder bumps and, in particular, into copper pillar bumps. The coefficient of performance (COP), or the ratio of the power pumped to the power supplied for heat pumping, is generally around 1 when thermoelectric material is placed in the package, but can reach 4, 6 or 8 when placed into a solder bump. This creates an attractive solution to a very vexing problem for the electronics industry.
The power/heat/efficiency trade-off
Examining projections of past power trends, a 20 GHz chip would consume and generate ~1 kW of power. Managing this power level in the laptop, PC or even server environment is simply not possible. Even more important is the fact that as the chip power increases, so does the power non-uniformity across the chip. The power profile over the surface looks like a mountain range, where the peaks represent the highest power density and highest temperature levels on the chip. In a low-power chip (35 W Intel Core Duo), the mountain range looks like gently rolling hills. On a high-power chip (>120 W), it may resemble the Himalayas.
Unfortunately, these mountain peaks have proportionally higher temperatures than the rest of the chip and represent a potential point of failure. If the circuit fails at the peak power point, the entire chip fails. These power non-uniformities are at all levels of the entire system. The failure to deal with them directly is the basis for all system-level inefficiencies.
On a typical circuit board, some of the chips are of high-average power and some are of low-average power. Consequently, the board represents a second stage for thermal non-conformity. Again, as circuit densities increase, overall power levels go up, environmental conditions get more demanding, and these non-uniformities become more challenging and deleterious to the health of the computer.
While power and thermal non-uniformities in electronics are constantly increasing, thermal management solutions have not evolved in lock step to effectively deal with these issues. Blowers and fans can be used to uniformly cool a computing system, but if the thermal profile is non-uniform, they will either undercool or overcool certain chips by default. Undercooling will lead to early failures and inherent inefficiencies as certain chips run too hot. Power MOSFETS on server boards, for example, do not experience the same level of cooling as CPUs do. As a result, they run too hot, generate more heat and run at a very low efficiency on the board. An alternative is to overcool, which is generally good for electronics, but leads to very low system-level efficiency and unacceptable energy expenditures.
The thermal management industry has responded to these issues by providing solutions in the formof heat pipes (to shift the heat away from high-power areas, such as at the CPU and GPU) and fans or heat sinks, which can provide localized thermal management to the highest-powered devices. While these solutions can be used to address the average thermal power coming off of a chip, they cannot address thermal non-uniformities within the chip. Even if these solutions were efficient, they are not scalable in two ways. First, they are bolt-on and not scalable to the entire chipset. Second, they cannot be scaled to handle the power levels that the most advanced chips can (achieving just 5°C of extra cooling on a typical chip requires a 2–4× increase in heat-sink size).
New approach
We developed a new approach to electronic thermal management that focuses on providing appropriate cooling where and when it is needed within the electronics system. This approach does not displace system-level cooling, which is still needed to move heat out of the system; rather, it introduces a fundamentally new methodology for achieving thermal uniformity at the chip and board level. In this manner, system-level thermal management will also become more efficient. As these solutions scale with the size of the system (bigger fans for bigger systems), this new approach scales at the chip level.
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| 1. Thermal and electrical bumps integrated on a single substrate. |
For each bump, thermoelectric cooling (TEC) occurs when current is applied. In other words, the thermal bump cools on one side and transfers heat to the other as current is passed through the material. This is known as the Peltier effect.
Thermoelectric power generation (TEG), on the other hand, occurs when the thermal bump is subjected to a temperature gradient (i.e., the top is hotter than the bottom). In this case, the device generates current, converting heat into electrical power. This is termed the Seebeck effect.
The thermal bump can be integrated as part of the standard flip-chip process (Fig. 1). As this functionality is integrated into the design and manufacturing infrastructure, chips will likely have a combination of both electrical bumps (for power, ground and signal) and thermal bumps (for cooling, temperature control and potential power generation). In this manner, the thermal bump offers new functionality to electronic product design. In the future, it will be possible to design thermal management into a circuit in the same manner that transistors, resistors and capacitors are integrated in conventional circuit designs today.
Copper pillar solder bumping
Recent trends in high-density interconnects have led to the development of copper pillar solder bumps (CPB).1 CPBs are an attractive replacement for traditional solder bumps in several ways. First, the pitch of the CPB is not dictated by a large volume of solder, but rather the size of the plated copper pillars. This leads to a much smaller pitch than traditionally seen with all-solder bumps. Second, the amount of solder needed to create a bump is substantially reduced because the majority of the interconnect volume is copper. In the case of lead-based solders, this reduces the lead volume, which is important for environmental concerns (RoHS compliance). Third, copper has a substantially higher thermal conductivity than most binary or ternary solders. For example, eutectic SnPb (63%Sn, 37%Pb) has a thermal conductivity of ~40 W/mK, as compared with 386 W/mK for copper. This means the CPB provides ~10× improvement in conductive thermal transport over traditional solder bumps of the same geometry. Fourth, because the copper pillars do not change shape during reflow, they are not susceptible to volumetric redistribution that can lead to voids (defects) in the solder bump that increase parasitic resistance and compromise reliability.
Thin-film thermoelectric technology
Thin-film thermoelectrics have been demonstrated to provide high heat-pumping capacity that far exceeds the capacities provided by traditional bulk pellet thermoelectric products.2 The benefit of thin films over thick bulk materials for thermoelectric manufacturing is expressed as:
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Here, the Qmax (maximum heat pumped by a module) is shown to be inversely proportional to the thickness of the film, L. As such, thermoelectric coolers manufactured with thin films can easily have 10–40× higher Qmax values for a given active area, A. This makes thin-film TECs ideally suited for applications involving high heat-flux. In addition to the increased heat pumping capability, the use of thin films allows for truly novel implementation of thermoelectric devices. Instead of a bulk module that is 1–3 mm in thickness, a thin-film TEC can be fabricated to <100 µm in thickness. In its simplest form, a P or N leg of a thermoelectric couple (the basic building block of all thermoelectric devices) is a layer of thin-film thermoelectric material with a solder layer above and below it to provide electrical and thermal coupling to electrical traces.
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| 2. Cross-sectional view of a thermal copper pillar bump. |
Thermal copper pillar bump
The thermal copper pillar bump (TCPB, Fig. 2) is compatible with the existing flip-chip manufacturing infrastructure, extending the use of conventional solder-bumped interconnects to provide active, integrated cooling of a flip-chipped component using the widely accepted CPB process. This process enhancement also enables power-generating capabilities within CPB for energy recycling applications.
The technology addresses thermal and power issues on-chip at their core. An analogy is a house with an overheated element on a kitchen stove. Rather than air conditioning the entire house to maintain the stovetop temperature, it would be much more efficient to locally and directly cool the overheating element. The TCPBs enable exactly this approach for electronic circuits. The result is higher performance and efficiency without higher system-level cooling, all within the existing semiconductor manufacturing paradigm.
This thermally active CPB has already demonstrated a number of world firsts: a temperature difference of 60°C has been achieved across the 60-μm-tall TCPB by running an electrical current through it; the TCPB demonstrated maximum power pumping capabilities exceeding 150 W/cm2; when subjected to heat, the TCPB has demonstrated the capability to generate up to 10 mW of power per bump.
Thermal copper pillar bump structureIn Figure 2, a SEM cross-section of a thermoelectric leg clearly shows that the thermoelectric element is structurally identical to a CPB with an extra layer, the thermoelectric layer, incorporated into the stack. The addition of the thermoelectric layer transforms a standard CPB into an active TCPB. This element, when properly configured electrically and thermally, provides active thermoelectric heat transfer from one side of the bump to the other side. Heat transfer direction is dictated by the doping type of the thermoelectric material (either an n-type or p-type semiconductor) and the direction of electrical current as it passes through the material (Peltier effect).3 Conversely, if heat is allowed to pass from one side of the thermoelectric material to the other, a current will be generated in the material (Seebeck effect). In this mode, electrical power is generated from the flow of heat in the thermoelectric element. The structure shown in Figure 2 can operate in both the Peltier and Seebeck modes, although not simultaneously.
A schematic comparing the structure of a typical CPB to a thin-film TCPB is shown in Figure 3. These structures are similar, with both having CPB and solder connections. The primary distinction between the two is the introduction of either a p- or n-type thermoelectric layer between two solder layers. The solders used with CPBs and TCPB can be any one of a number of commonly used solders, including, but not limited to, SnPb eutectic, SnAg or AuSn.
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| 3. Schematic showing traditional CPB next to a P-type and N-type pillar bump. The p- and n-type bumps together make up a P/N couple that, when connected in a series electrically, provides for either Peltier cooling or Seebeck power generation. |
An expanded view of a TCPB is shown in Figure 4. Several additional attributes of this design are depicted. First, thermal flow in the device is illustrated by arrows labeled "heat." Heat flow through the TCPB may be assisted by the design of the metal traces on the chip. These traces, which can be several micrometers in thickness and can be stacked interdigitated, provide highly conductive pathways for collecting heat from the underlying circuit and funneling that heat to the TCPB.
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| 4. This close-up schematic shows flow of heat through a TCPB. Also shown are the multilayer metal traces often used in complex ICs. These metal layers are beneficial for gathering heat from larger areas and funneling it into the TCPB, reducing the thermal constriction resistance in the circuit. A thermal via is shown in the PCB for improved heat rejection. |
The metal traces shown in Figure 4 for conducting electrical current into the TCPB may or may not be directly connected to the circuitry of the chip. In either case, on-board temperature sensors and driver circuitry can be used to control the TCPB in a closed-loop fashion for optimal performance. Second, the heat that is pumped by the TCPB and the additional heat created by it in the course of pumping the heat are rejected in the substrate or board. Because the performance of the TCPB can be improved by providing a good thermal path for the rejected heat, it is beneficial to provide high thermally conductive pathways on the backside of the TCPB. The substrate might be a highly conductive substrate like AlN or a metal (i.e., copper, CuW, CuMo, etc.) with a dielectric. In this case, the high thermal conductance of the substrate will act as a natural pathway for rejected heat. The substrate might also be a multilayer substrate, such as a printed circuit board (PCB), designed to provide a high-density interconnect. In this case, thermal conductivity of the PCB may be relatively poor and adding thermal vias (i.e., metal plugs) can provide excellent pathways for the rejected heat.
Applications
Because TCPBs are similar in structure and use comparable processing techniques to those used for manufacturing traditional CPBs, the implementation of these structures can be readily integrated into existing CPB-based processes.
TCPBs can be used in a number of different ways to provide chip cooling, including:
- General cooling — TCPBs can be evenly distributed across the surface of a chip to provide an evenly distributed cooling effect. In this case, the TCPBs may be interspersed with standard CPBs that are used for signal, power and ground. This allows the TCPBs to be placed directly under the active circuitry of the chip for maximum effectiveness. The number and density of TCPBs are based on the heat load from the chip. Each P/N couple can provide a specific heat pumping (Q) at a specific temperature differential (T) at a given electrical current. Temperature sensors on the chip ("on-board" sensors) can provide direct measurement of the TCPB performance and provide feedback to the TEC driver circuit.
- Precision temperature control — Because TCPBs can either cool or heat the chip, depending on the current direction, they can be used to provide precision control of temperature for chips that must operate within specific temperature ranges irrespective of ambient conditions. For example, this is a common problem for many optoelectronic components.
- Hot spot cooling — In microprocessors, GPUs and other high-end chips, hot spots can occur as power densities vary significantly across a chip. These hot spots can severely limit the performance of the devices. Because of the small size of the TCPBs and the relatively high density at which they can be placed on the active surface of the chip, these structures are ideally suited for cooling hot spots. In such a case, the distribution of the TCPBs may not need to be even. Rather, the TCPBs would be concentrated in the area of the hot spot while areas of lower heat density would have fewer TCPBs per unit area. In this way, cooling from the TCPBs is applied only where needed, thereby reducing the added power necessary to drive the cooling and reducing the general thermal overhead on the system.
In addition to chip cooling, TCPBs can be applied to high heat-flux interconnects to provide a constant, steady source of power. Such a power source, typically in the mW range, is ideal for trickle charging batteries for wireless sensor networks and other battery-operated systems.
| Author Information |
| Phil Deane is a Senior Technology Fellow at Nextreme Thermal Solutions. He has over 25 years' experience in electrical interconnect technology, semiconductor processing and package development. Deane holds a Ph.D., M.S. and A.B. in physics from the University of North Carolina (Chapel Hill). |
| References |
| 1. J. Kloeser et al, "High-Performance Flip-Chip Packages With Copper Pillar Bumping," Global SMT & Packaging, May 2006. |
| 2. G.J. Synder et al., "Hot Spot Cooling Using Embedded Thermoelectric Coolers," Proc. 22nd IEEE Semi-Therm Symposium, 2006. |
| 3. D.M. Rowe, ed., CRC Handbook of Thermoelectronics. Boca Raton, CRC Press, 1994. |
