Industry News
Staff -- Semiconductor International, 3/1/2008
TI Pushes Junctions in 45 nm Transistors
Researchers at Stanford University (Palo Alto, Calif.) have developed a method of placing multi-walled carbon nanotubes (MW-CNTs) as wires, with gigahertz-level interconnect performance observed for the first time.
H.-S. Philip Wong, the Stanford electrical engineering professor who supervised the work by doctoral student Gael Close, said, "Until now, there has been very little experimental verification of nanotube wiring in a digital circuit, though there has been a lot of anticipation that nanotubes could work as interconnects. This convinces us that using nanotubes for wiring is a promising approach."
The project also involved several Toshiba Corp. (Tokyo) researchers who designed a ring oscillator test chip to determine the nanotube interconnect performance. The 0.25 μm test chip was fabricated at Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) and then returned to the Stanford Nanofabrication Facility, where the CNTs were connected. The solution of nanotubes was provided by Helix Material Solutions Inc. (Richardson, Texas).
Details were published in NanoLetters. The challenge involved fixing the tubes to a CMOS circuit. Growing the tubes in place was out of the question: nanotube growth requires ~800–900°C temperatures, which would melt a CMOS chip.
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| TI's 45 nm NMOS (left) and PMOS transistors use abrupt junctions and 38 nm gate lengths, while keeping leakage at a minimum. |
To place the tube, Close devised a placement technique that employed the dielectro-phoretic effect. Gold electrodes were created in pairs, and an alternating current (AC) field was created across the two electrodes. A solution containing the CNTs was dropped in place. The ~200 kHz AC field attracted one of the long, thin nanotubes (~5 μm in length and ~50–70 nm in diameter), causing the tube to line up and bridge the two electrodes.
"Once the tube bridges the electrodes, it disturbs the electric field pattern immediately around it, which then no longer attracts any more nanotubes. That is how we have one tube for each electrode pair," Wong said.
The speed of the nanotube interconnects was tested by building a 11,000-transistor CMOS device with 256 ring oscillators, each with one level of wire missing, and then placing the tube on top of the electrodes. The packaged test chip was wired up to a PCB and tested to show that digital signals can pass through the circuits at gigahertz-level speeds.
Wong said simulations by professors Jim Meindl of the Georgia Institute of Technology (Atlanta) and Krishna Saraswat of Stanford have shown that CNTs theoretically should be capable of terahertz-level interconnect performance. However, Wong said that previous demonstrations have been relatively slow, mainly due to large on-chip capacitances and some off-chip test elements.
"To have a very high frequency signal, you need to have very small capacitance on the chip. With this experiment, everything was on-chip, and we have very small, femtofarad-level capacitances, which is compatible with the speed you are trying to drive to," Wong said.
While CNTs in very small diameters can be either metallic or semiconducting, the tubes with relatively large diameters used for interconnects are almost always metallic, he said. "It still is hard to control the insulating or metallic properties of the small-diameter nanotubes required for digital switching. For interconnects, it is different. Typically, the bandgap of a nanotube is inversely proportional to the diameter. The larger the diameter, the smaller the bandgap. With the large-diameter tubes, the bandgap is almost zero, which means that it is conducting," Wong said.
However, the CNT resistance level can be several times higher than copper, requiring more work to improve the purity of the tubes.
An advantage of CNTs is that they are resistant to the electromigration (EM) effects seen in small-diameter copper wires. EM causes copper atoms to move in the opposite direction of the current passing through the wire. If enough copper atoms move out of place, a void is created and the wire fails.
Wong said the main challenge with CNT interconnects is to come up with a set of integrated processes to put the tube on top of the CMOS chip at high yields. "We used a very small chip, only 5 mm on a side, and we have to do 4–5 levels of lithography on top. If we do it on a wafer, that shouldn't be so much of a problem," he said.
The Stanford project is being supported with a three-year grant from the MARCO Interconnect Focus Center. Wong said Close is already working to reduce the diameter of the CNT interconnects and improve the yields. In the first experiment, 19 of the 256 CNT interconnects successfully operated, an ~8% rate. Also, the team wants to demonstrate more complex circuits, with more than one nanowire in the same circuit.
— David Lammers, News Editor
Photovoltaics: Grid Competitive in Five Years
The solar photovoltaic industry will achieve grid parity — standalone economic viability without incentives — in under five years. This prediction was made by Stephen O'Rourke, senior analyst covering semiconductor capital equipment and materials for Deutsche Bank Securities (New York, N.Y.), at the Industry Strategy Symposium (ISS 2008), presented by SEMI and held in Half Moon Bay, Calif.
"This time, the solar PV industry won't fall back into obscurity as in the past," O'Rourke observed. "The technologies that exist today to generate electricity from photovoltaics are several: crystalline silicon and several thin-film approaches." The graph around which the presentation was built displayed curves representing the different technologies available to generate electricity using solar power. The curves started in 2006 and were extrapolated to 2020. "The defining metric of what's competitive in this industry is the declining cost per kilowatt-hour," O'Rourke said. "It's all about selling energy; not about cells or modules or systems."
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| Projection of PV electricity prices and potential grid-parity points. (Source: Deutsche Bank Securities) |
O'Rourke looked at the average cost of grid electricity for 2006 — 8.6¢/kWh, a blended average in the United States — considering an aggregate growth rate of ~4.5% over the past seven years. He then extrapolated those growth rates into the future. "This provides us with a time frame for convergence — when solar becomes competitive with grid-supplied electricity. This happens when it gets below the average retail cost of grid electricity," he said, adding that these were conservative numbers.
According to O'Rourke, supply and demand is the linchpin of the solar photovoltaic industry. "Considerable capacity is being built, because there's a supply constraint due to an inadequate supply of refined silicon. Currently, because there is an undercapacity, things look very good, margins are great, and companies are profitable. However, that will soon lead to an oversupply situation, probably beginning in 2009, when there will be a more than adequate supply of polysilicon." He that this will not be what he defines as a "persistent" oversupply, but one governed by demand elasticity. "It's akin to the memory industry — prices fall, margins compress, stocks come down, balance sheets are challenged, and there is a shakeout in the industry," he said. "I estimate this will last for a couple of years."
O'Rourke stressed that he was being conservative in his predictions, particularly because it is impossible to factor the appearance of a new technology. "When new technologies step into an industry, they can alter the entire dynamic, change the cost-reduction curve," he said. "I don't anticipate this within the next five years. But if we have such a shakeout, all the cost curves can get shifted down and bring convergence much sooner." However, O'Rourke was careful to point out that when photovoltaics reach grid parity, the technology will still be used as a peak power supplement, not a base load supplement. "But photovoltaics are a real industry now, and one that will have explosive growth once it reaches that convergence point." The analyst described photovoltaics as the oldest new industry because it has been around for half a century. "It is now in an initial growth phase. We've seen enormous funding of new capacity growth, new companies and new issues coming to market. I think we're on the downswing of this as we start to anticipate an oversupply situation. This has happened both for crystalline silicon and thin-film technologies," he said.
— Alexander E. Braun, Senior Editor
EUV Research Helps Solve 193 nm Resist Problems
Leading-edge research into the requirements for extreme ultraviolet (EUV) photoresists is helping to solve some of the problems encountered by 193 nm lithography technology as it ventures into increasingly smaller CDs.
Robert Brainard, an associate professor at the College of Nanoscale Science and Engineering (CNSE) at the University at Albany in New York, is investigating new materials for use in EUV and 193 nm lithography. While the bulk of the work that he and his group are conducting is focused on EUV photoresists, it has also dealt with some of the problems encountered at 193, which are becoming very similar to those for EUV.
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| Large jumps in resist performance require the pursuit of discontinuous variables, such as synthesis of new materials. Resist performance must then be optimized within the new multidimensional performance surface. (Source: CNSE, University at Albany) |
According to Brainard, one can take a simple resist and measure its line-edge roughness (LER) and sensitivity, and then perhaps add more base to it. However, when this is done, the resist slows down. "These are chemically amplified resists, so the light generates acid. If you add more base, it kills the acid and then you require more light," Brainard said. The result is, however, that by adding the base, LER is reduced, resulting in smoother lines. Conversely, if the base is reduced, the resist becomes more sensitive, but LER worsens.
"In both cases you want a lower number — you want lower LER and a lower dose [sensitivity is measured in millijoules per square centimeter]. This means that the resist is sensitive," Brainard said. "There are trade-offs for all three different properties. This, in my thinking, is EUV resist's principal challenge — beating the trade-offs. I look at the problem much like a curved surface, where you can move around on it and trade one performance factor for another, but you do not get off the surface. What we want to do is invent something that will enable us to leave that surface." Both 193 nm and EUV resists now face similar fundamental problems. "The industry has attributed those problems to EUV, simply because EUV reached those dimensions earlier — it uses shorter wavelengths," Brainard said. "Meanwhile, 193 has continued advancing toward smaller dimensions, and it is reaching the CD size regime where the technology is beginning to face, or will soon face, the same problems."
One of these hurdles is controlling acid diffusion. There may be ways to solve this that have not yet been tried, which are being developed at CNSE; however, because of intellectual property (IP) concerns, Brainard declined to be specific. "In terms of the RLS trade-off, there is need to make more acid. The more efficient you are in producing the acid, the better the performance gets," he said.
"We're learning from EUV technology things that are directly applicable to 193. At the 22 nm node, whether it is 193 that gets there or EUV, there are fundamental problems in the understanding of things like acid diffusion that have to be solved by whichever resist technology is used."
— Alexander E. Braun, Senior Editor
3-D Analysis Progressing to Meet Device Needs
Although there are several tools and concepts available, the analysis of ultrashallow junctions (USJs) is increasingly becoming an unavoidable problem requiring resolution. "The Holy Grail in this area of metrology is being able to produce a complete 3-D profile — dopant and carrier — for a device," said Wilfried Vandervorst, head of the Materials and Components Analysis group of IMEC's (Leuven, Belgium) Process Technology Division. "As planar devices are replaced by 3-D structures, metrology tools capable of probing the dopant or carrier distribution of, for instance, a finFET, become necessary. These should be capable of providing sensitivity, quantification, accuracy, reproducibility and spatial/depth resolution data comparable to today's 1-D and 2-D tools."
IMEC has devoted a decade-long effort to 2-D and 3-D analysis using various probe technologies. "Particularly in our 2-D work, our major accomplishment has been breaking the nanometer barrier; we are now down to ~300 picometers in terms of spatial resolution," Vandervorst said. "This enables us to look at even smaller structures enabling us to see the 3-D dopant distribution inside a transistor, which requires extremely precise measurements to determine the overlap, the effective channel length — basically, the transistor's heart, wherever the dopants are located." At the 22 nm node, the dimensions Vandervorst refers to are at the nanometer level. Their importance is out of proportion to their size, requiring extremely high spatial resolutions to be able to measure them with the requisite high precision.
"We've accomplished a major improvement by going from measurements in air to measurements in vacuum," Vandevorst stated, "which solves many problems by allowing measurements to be run at lower probe forces, and providing more reliable results and better spatial resolution." While this is a considerable achievement in the 2-D metrology space, the quantum leap being pursued is being able to do this in 3-D for devices such as finFETs. As Vandervorst put it, "With 2-D, you can take a transistor, cross-section it and measure it right there on the cross-section. This works very well. However, when you are dealing with a 3-D device, it becomes impossible to do that kind of measurement. Consider that the gate of a finFET would be 50 nm — how do you cross-section a 50 nm gate?"
The illustration shows this 3-D structure and indicates how far the dopants can distribute underneath the gate. "The whole thing is some 10 by 50 nm," Vandervorst said. "Within those 10 nm, you face extremely difficult spatial resolution problems and confinement problems because you are getting down to dimensions where the number of atoms is limited — maybe five dopant atoms in one transistor. It is clear that the accurate positioning of junction depths and the measurement of lateral interdiffusion will require very advanced averaging and statistical data analysis to achieve meaningful results. We are developing a system that'll enable 3-D measurements at an atomic scale. This is an electrical measurement, and there is a counterpart in atomic probe measurement where we are counting atoms. For the future, everything comes down to be able to measure extremely small volumes with 3-D space resolution — electrically as well as chemically."
Although inevitable, going to 3-D using an atomic probe is not going to be a simple matter. Yet to be determined are the methodology, physics and the quantification that are needed to make this metrology technology work. IMEC expects to have results using atomic probes in 1–1.5 years. The researchers are in the process of exploring scanning probe concepts, and expect to have good results within that same time period.
— Alexander E. Braun, Senior Editor
CNT-Based Interconnects Go GHz
Researchers at Stanford University (Palo Alto, Calif.) have developed a method of placing multi-walled carbon nanotubes (MW-CNTs) as wires, with gigahertz-level interconnect performance observed for the first time.
H.-S. Philip Wong, the Stanford electrical engineering professor who supervised the work by doctoral student Gael Close, said, "Until now, there has been very little experimental verification of nanotube wiring in a digital circuit, though there has been a lot of anticipation that nanotubes could work as interconnects. This convinces us that using nanotubes for wiring is a promising approach."
The project also involved several Toshiba Corp. (Tokyo) researchers who designed a ring oscillator test chip to determine the nanotube interconnect performance. The 0.25 μm test chip was fabricated at Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) and then returned to the Stanford Nanofabrication Facility, where the CNTs were connected. The solution of nanotubes was provided by Helix Material Solutions Inc. (Richardson, Texas).
Details were published in NanoLetters. The challenge involved fixing the tubes to a CMOS circuit. Growing the tubes in place was out of the question: nanotube growth requires ~800–900°C temperatures, which would melt a CMOS chip.
 |
| The researchers used single CNTs to create one level of wiring on a test chip containing ring oscillators. |
To place the tube, Close devised a placement technique that employed the dielectro-phoretic effect. Gold electrodes were created in pairs, and an alternating current (AC) field was created across the two electrodes. A solution containing the CNTs was dropped in place. The ~200 kHz AC field attracted one of the long, thin nanotubes (~5 μm in length and ~50–70 nm in diameter), causing the tube to line up and bridge the two electrodes.
"Once the tube bridges the electrodes, it disturbs the electric field pattern immediately around it, which then no longer attracts any more nanotubes. That is how we have one tube for each electrode pair," Wong said.
The speed of the nanotube interconnects was tested by building a 11,000-transistor CMOS device with 256 ring oscillators, each with one level of wire missing, and then placing the tube on top of the electrodes. The packaged test chip was wired up to a PCB and tested to show that digital signals can pass through the circuits at gigahertz-level speeds.
Wong said simulations by professors Jim Meindl of the Georgia Institute of Technology (Atlanta) and Krishna Saraswat of Stanford have shown that CNTs theoretically should be capable of terahertz-level interconnect performance. However, Wong said that previous demonstrations have been relatively slow, mainly due to large on-chip capacitances and some off-chip test elements.
"To have a very high frequency signal, you need to have very small capacitance on the chip. With this experiment, everything was on-chip, and we have very small, femtofarad-level capacitances, which is compatible with the speed you are trying to drive to," Wong said.
While CNTs in very small diameters can be either metallic or semiconducting, the tubes with relatively large diameters used for interconnects are almost always metallic, he said. "It still is hard to control the insulating or metallic properties of the small-diameter nanotubes required for digital switching. For interconnects, it is different. Typically, the bandgap of a nanotube is inversely proportional to the diameter. The larger the diameter, the smaller the bandgap. With the large-diameter tubes, the bandgap is almost zero, which means that it is conducting," Wong said.
However, the CNT resistance level can be several times higher than copper, requiring more work to improve the purity of the tubes.
An advantage of CNTs is that they are resistant to the electromigration (EM) effects seen in small-diameter copper wires. EM causes copper atoms to move in the opposite direction of the current passing through the wire. If enough copper atoms move out of place, a void is created and the wire fails.
Wong said the main challenge with CNT interconnects is to come up with a set of integrated processes to put the tube on top of the CMOS chip at high yields. "We used a very small chip, only 5 mm on a side, and we have to do 4–5 levels of lithography on top. If we do it on a wafer, that shouldn't be so much of a problem," he said.
The Stanford project is being supported with a three-year grant from the MARCO Interconnect Focus Center. Wong said Close is already working to reduce the diameter of the CNT interconnects and improve the yields. In the first experiment, 19 of the 256 CNT interconnects successfully operated, an ~8% rate. Also, the team wants to demonstrate more complex circuits, with more than one nanowire in the same circuit.
— David Lammers, News Editor
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