What's Delaying the Adoption of 3-D TSV?
Jan Vardaman, President, TechSearch International Inc., Austin, Texas, www.techsearchinc.com -- Semiconductor International, 3/1/2008
 |
Expectations for the technology are running high, but many industry participants are waiting for mass production. When is it advantageous to go vertical and when is it not? Stacking two wafers together and integrating them with vertical vias is not inexpensive. This cost must be justified through performance gains, functional gains, or cost savings elsewhere in the system. So when will the market develop?
The market for TSV will be established when the benefits justify the cost, and on a case-by-case basis. There is a growing consensus that there are several mainstream circumstances that justify 3-D integration. 3-D TSV will become a reality — when is the question.
Miniaturization is one driver. Today's adoption in image sensors for camera modules is the first high-volume application using TSV technology, with production lines already installed at Toshiba, Oki Electric and other companies. However, for most applications, TSV is rarely justified by the desire for miniaturization alone. If volume reduction is the only goal, then it is much more cost-effective to stack and wire bond, or otherwise vertically integrate, at the package level. The technology is in widespread use in cell phones, and continues to grow in sophistication. The cost of wire bonding is relatively low. While Samsung has made an argument for the adoption of TSV for NAND flash, other companies argue that the cost of TSV cannot be justified and the required density can be obtained by thinning the die and wire bonding the stack. TSV technology for NAND flash is not expected to be used in high volume until 2012 or later.
While many DRAM makers have developed demonstration TSV products, the first commercial application for DRAM with TSVs is not expected until 2010 for the server market. The first stacked processors on DRAM with TSV are not expected until after 2014. Field-programmable gate arrays (FPGAs) may not use TSVs until as late as 2013, depending on resolving the issues with known good die (KGD), cost and yield.
Barriers to adoption
Even with the advantages of 3-D ICs, there are several challenges to the adoption of 3-D architectures. These challenges need to be overcome for the technology to see widespread adoption:
- Commercial availability of EDA tools and design methodologies
- Thermal concerns caused by the increased power densities
- Test, especially for repartitioned logic
3-D integration technology will not become commercially viable without the support of EDA tools and methodologies that will allow circuit designers to use the technology. Design tools remain a weak link in the 3-D infrastructure, with better thermal modeling, finite-element analysis, floor planning, and layout tools all required for smooth 3-D design flows. Current design tools used for 2-D ICs cannot be easily extended to 3-D ICs.1
The move to 3-D architectures could accentuate the thermal problem in many applications. There have been numerous accomplishments; however, solutions such as thermal vias take up valuable space.
Many companies have not sufficiently investigated the test issues associated with the adoption of TSV for more complicated devices in a production environment. Researchers assume that KGD will be available, but test methods are still in development and little has been published.
Conclusions
There is no question that 3-D TSV will be adopted, but the timing for mass production depends on how the TSV technology compares in terms of cost with existing technologies. Image sensors for camera modules are already in volume production. For other applications, the adoption is longer than originally imagined, as is common with the introduction of new technologies. While progress is being made, design, thermal and test issues remain a barrier to TSV adoption in some applications.
| Reference |
| 1. Y. Xie, G. Loh, B. Black and K. Bernstein, "Design Space Exploration for 3-D Architectures," ACM J. on Emerging Technologies in Computing Systems, 2006, Vol. 2, No. 2, p. 65. |
