3-D Gets Past 'Chicken or Egg' Problem

When IMEC (Leuven, Belgium) announced its expanded programs in 3-D at its annual meeting last year, Eric Beyne, scientific director of packaging, interconnect and systems integration, admitted that "3-D design suffers from a 'chicken or egg' problem." Users that are evaluating the cost trade-offs of 3-D integration need design tools to evaluate the benefits of manufacturing in 3-D (z direction) vs. 2-D. However, the EDA community will not supply such tools until there exists a specific and large market for 3-D design tools. Jan Vardaman of TechSearch International (Austin, Texas), who consults on the adoption of 3-D technology, agrees that commercial availability of design tools and methodologies for 3-D are a key challenge that must be overcome for 3-D to enjoy mainstream adoption (see "What's Delaying the Adoption of 3-D TSV?"). She cites management solutions for the thermal issues (increased power densities) and production test solutions as two other key infrastructure challenges needed to speed along the 3-D engine. Even so, Vardaman believes that through-silicon vias (TSVs) for stacked chip applications are likely to be in production by 2010 (see "Through-Silicon Vias: Ready for Volume Manufacturing?").

I liken this 3-D integration situation to that of the early MEMS market, when accelerometers for air bags were the first high-volume killer application in MEMS. Obviously, there were no commercial design tools and methodologies in place for putting these sensors in a suitable package, so the manufacturers had to specifically develop design tools and packaging methodology. In the TSV world, the first volume-production application was the manufacture of CMOS image sensors for digital video cameras. This approach uses a via-last process, where interconnects are formed after the back-end-of-line (BEOL) device process is through. Via-last means that an outsourced semiconductor assembly and test company typically provides the through-substrate via interconnects.

This volume application has driven maturation of some of the first process tools specifically targeting TSV etching and subsequent deposition techniques, as Pete Singer outlines in the cover story this month. The article explores the industry's movements toward via-first approaches and, more importantly, reducing costs.

Gone are the days when a technology would be developed for technology's sake. In fact, there are multiple drivers for TSV based on 3-D integration, one of the main ones being cost. As Fred Roozeboom, Research Fellow at NXP Semiconductors Research (Eindhoven, Netherlands), stated at IMEC's meeting, they expect a large cost difference between 2-D (planar CMOS) and 3-D approaches at a flash capacity of >64 Gb.¹

IMEC's Diederik Verkest added that a 45 nm 3-D approach could prove less expensive than bringing 32 nm planar devices to market.

And speaking of design rules, one of the interesting challenges for TSV technology is the difference in design rules that must be achieved for different applications. As described by Steve Lassig, senior engineering manager at Lam Research, there is almost two orders of magnitude of difference in feature sizes for TSVs in development. At one extreme, companies are requesting processes with 90 μm vias, 400 μm deep, while others are looking to make 1 μm vias ~10 μm deep. Somehow, packaging houses, with relatively low-tech physical vapor deposition (PVD) equipment for processing the barrier and seed via deposition vs. the semiconductor manufacturers with the most leading-edge equipment, will each provide the via-last and via-first processes, respectively, for different applications.

IMEC breaks down the 3-D integration possibilities into 3-D system-in-packaging approaches (package-on-package [POP] connected by wire bonds), 3-D wafer-level packaging (WLP, connected at the bump and distribution layer), and 3-D wafer-level IC (connected by TSVs). Increasingly, 3-D refers to the latter two approaches. Benefits to each include packing density, smaller form factor, reduced signal delays and, ultimately, the ability to efficiently integrate devices with different functions (heterogeneous integration).

So, the answer to which came first — the 3-D integrated devices (chickens) or the design approaches (eggs) — seems fairly clear at this point. Both are being developed in tandem, perhaps best exemplified by our article on an integrated platform for integrating passive and active devices for wireless applications (see "Technology Platform Integrates High-Performance SiP Modules"). Without a defined platform, devices will not be integrated, and without a very strong driver (handheld, wireless communication), there's no need for the platforms. Join us as we follow this dynamic, exciting next step of semiconductor manufacturing in the third dimension.