Fab-Wide SPR Speeds Yield Improvement

Quickly identifying and correcting yield-robbing problems is critical to profitable semiconductor manufacturing. To help achieve this goal, manufacturers are using increasingly sophisticated measurement, inspection and test systems to monitor the hundreds of process steps required to build IC devices. These systems gather wafer data and flag major process excursions, but they can miss more subtle defects that, over time, substantially affect yield. Intelligent mining of the enormous amount of available data is needed to speed problem identification and improve root-cause analysis (RCA). Automated spatial pattern recognition (SPR), which identifies clusters of defects on the wafer, can provide a solution. However, to be effective, SPR technology must be fast, accurate, scalable and have the capability to process multiple data types from various sources.

AMD worked with Rudolph Technologies to develop and deploy an advanced SPR system. The challenges encountered and advantages gained are discussed here.

Background

SPR is a well-known technique to organize yield data for RCA. The spatial patterns are clusters — non-random groupings — of defective die on a wafer. What constitutes a defective die depends on the type of test being performed and, therefore, can be based on defect, sort or parametric data. The patterns are generally attributable to misprocessing by a specific chamber, tool or process step, so recognizing the pattern is the first step toward isolating and correcting the yield-robbing problem. Figure 1 shows the clear relationship between yield loss and the total area of clustered defects.

1. Yield decreases as the total area of clustered (non-random) yield loss increases. Therefore, quickly identifying and correcting the cause of defect clusters can substantially improve yield.

Historically, SPR has been performed by small groups of fab engineers or technicians skilled at identifying defect patterns and determining their root cause. However, human inspectors are comparatively slow and can review only a tiny fraction of the wafer data generated by a modern fab. Humans are also inconsistent when it comes to classifying defect patterns. Internal AMD studies have shown that classification matching rates between two human experts may be as low as 45%. To further complicate matters, departments within the fab may name similar patterns differently, making fab-wide SPC or RCA difficult. Finally, human inspectors tend to miss subtle patterns that can indicate the beginning of a problem or may significantly affect yield over time.

To address the deficiencies of human inspectors, a variety of automated pattern recognition tools have been deployed in semiconductor manufacturing. These tools have gone by a variety of names, with the most common synonym for SPR being spatial signature analysis (SSA). These SPR/SSA tools have had the advantage of being faster and more consistent than humans. However, their usefulness was limited for several key reasons. The tools generally were exclusive to a particular type of data, such as inspection or sort, and, therefore, could not be used throughout the fab. Additionally, defining and maintaining the pattern libraries for pattern classification was complex and labor-intensive, and the libraries had to be rebuilt for different wafer sizes, die or technologies so the tools could not be used company-wide. Finally, while the tools were good at recognizing and classifying simple patterns, such as scratches, they were ineffective with more complex patterns or in detecting multiple patterns on a single sample.

AMD determined that they needed a versatile, high-volume SPR system to help improve yield. An automated system was required, as larger wafer sizes, faster processing tools, and more measurement, inspection and test steps have led to an exponential increase in the amount of data available for yield analysis. The system also needed to:

• handle multiple data types, including defect, sort and parametric
• process defect wafer maps very quickly, on the order of a few seconds per map
• offer accurate and repeatable pattern classification
• work with multiple wafer sizes, die types, technologies, etc.

Identifying defect patterns

The SPR engine consists of two main components: identifying defect patterns from wafer maps and building the classification library. In addition, a database stores the pattern information on a wafer and lot level so that the data can be easily retrieved for analysis.

The first step in recognizing defect patterns is to load a wafer map that identifies "good" and "bad" die into the SPR engine. Good and bad must be predefined based on the type of data. For example, in the sort wafer map shown in Figure 2, in Step 1, the SPR engine automatically assigns a good or pass rating to the green die and a bad or fail rating to the others. The map is then digitized with only the bad die identified in red, as shown in Step 2. The SPR system is designed to work with wafer maps from any source, requiring only that good/bad or pass/fail criteria can be clearly determined.

2.  The SPR engine separates the failed die into random and periodic wafer characteristics. The larger cluster groups are identified, then uniquely classified from an established pattern library. These results are stored in a database.

The digitized map is then analyzed to determine if the bad die are randomly or periodically distributed. If no significant spatial patterns are found, the process ends and the wafer information is stored in the database with a generic classification. Otherwise, noise reduction and pattern enhancement filters are applied to isolate the defect clusters. For the sort wafer example, the different clusters are shown in Step 3. The clusters have different colors to simplify visualization. The last step compares the identified defect patterns with those in the library and classifies them accordingly. The pattern names and their level of confidence are shown in Step 4. Note that the blue pattern in the upper right does not match any existing categories and is stored as an unknown pattern with a unique ID. This unknown pattern can be retrieved and named at a later date.

Building the pattern library

Developing a robust library is challenging because each manufacturer, fab or department may classify a similar spatial pattern with a different name; to further complicate matters, the library must be valid across multiple wafer sizes, technology nodes, device types, yield ranges and data types. Therefore, it is crucial that defining new patterns be fast and easy, classification names are simple and clear, and extensive user-friendly library diagnostics are available.

3. The pattern shown in rust can be subjectively named as a ‘happy face.’ However, for clear naming conventions that can be easily understood, it is preferable to identify this pattern as a ring-arc bottom with clusters in the upper left and right quadrant.

At AMD, more than 50 specific patterns were identified and named. These were generated from ~600 individual samples. The patterns were broken into nine general groups to simplify use, including band, center, edge, quadrant, ring, and streak.

SPR engine performance

In deployment tests, the SPR engine was able to process up to 1200 wafer maps per hour with pattern classification accuracy and purity >80% across a wide variety of conditions:

• 200 and 300 mm wafers
• die sizes ranging from 85 to 210 mm²
• multiple device types
• data types, including sort (bin, DC, and pass/fail) and front side, edge normal, and backside defect

In addition, preliminary tests using metrology data have proven successful and will be deployed in 2008.

The SPR engine can process over 10 million wafer maps per year. The challenge is to use the data effectively; otherwise, the SPR system will just add to the wafer data proliferation problem instead of providing a solution. The key is how the SPR data is collected and stored. At the wafer level, the pattern names, sizes and confidence levels are stored in the database. The individual wafer information is then rolled up to a lot level where the total amount of material affected by each pattern and the average value for pattern size and confidence are also stored.

The data is then analyzed with trend charts in a similar fashion to any other wafer- or lot-based parameter. Variables that can be charted can include:

• frequency of pattern occurrence
• amount of material impacted by the pattern
• confidence of the pattern

An upper control limit is set to identify wafers or lots where a specific variable falls outside the normal distribution. This can generate a hundred or more trend charts for a particular process being analyzed, so the SPR engine provides tools to quickly identify and notify technicians when out-of-control conditions are found. In a lot-level trend chart, several outliers can be seen in the last half (Fig. 4). This indicates a problem that should be investigated.

4. The upper control limit is shown in green. Here, the trend is increasing, with five lots in the second half of the data exceeding the limit. The source of this out-of-control condition needs to be investigated to prevent further yield loss.

In addition to identifying excursions, the wafer- and lot-level information from all wafer maps processed is searchable based on user-specified constraints. These constraints can be used to identify samples to define a new pattern classification or, once a new pattern has been defined, the data can be searched to find other instances of the pattern to help determine the root cause. A unique feature enables correlation of patterns so if, for example, a pattern is found in sort, the user can look for a similar pattern in the defect or parametric data to help isolate the process step where the problem occurred.

Using the SPR engine to track the incidence of spatial patterns in production has proven an effective technique to quickly find and correct yield-robbing problems. Three typical examples follow.

Lot-by-lot analysis — The SPR engine generates lot-level trend charts that track the amount of material affected by a pattern (Fig. 4). When multiple lots exhibit high levels of a certain pattern, this can often be traced back to misprocessing by a process tool. In one case, a high level of wafer edge defects was found in the lot-to-lot trend charts. The SPR system identified the problem and lots affected. Fab engineers then used engineering data analysis (EDA) techniques — in this case, find relationships — to determine that only lots being processed by a specific tool were exhibiting the defect. The tool was repaired and the yield-robbing problem resolved.

Within-lot variation — When an out-of-control pattern condition is found in an individual lot, the SPR engine can drill down to the wafer level to help identify the problem's source. In the case shown in Figure 5, the lot exhibited a strong signal for center good (and edge bad). When the stored wafer-level data was analyzed, it was found that only about a quarter of the wafers in the lot exhibited this pattern, while the others did not. A wafer positional analysis system determined that every fourth wafer in the cassette was affected. This allowed the problem to be traced back to a bad etch chamber.

5. This lot demonstrated high levels for the center good pattern. To investigate, the data from the individual wafers (shown at bottom) was retrieved from the database. The wafers in cassette positions 2, 3 and 4 were fine, but the wafers in position 1 had poor yield at the edges. Using this information, the root cause of the problem was determined to be a faulty etch chamber.

Searching multiple lots — When a new or unusual pattern that reduces yield is found, the SPR engine can search through its database to find similar patterns in wafers or lots that have already been processed. This can significantly narrow the search for the root cause, as only the process steps that all of the wafers or lots shared must be investigated. Recently, several wafers exhibited very low yield in the lower-left quadrant. This pattern was inputted into the SPR search engine. Given the particular search parameters, 36 wafers across 20 lots were identified with a high level of confidence as matching the pattern. The list of wafers was exported to several EDA systems, and a positional frequency plot for a batch tool indicated that this was a top-of-the-boat problem. As in the previous examples, once the source of the problem was identified, it was fixed and yield was improved.

The challenge of SPR technology is to deploy an SPR system that is able to effectively process the enormous amount of data generated in modern fabs, and then organize that data for fast and consistent problem solving. The SPR system co-developed by AMD and Rudolph Technologies has demonstrated these capabilities with its high-speed, accurate classification, ability to work with various data types, and its sophisticated analysis and search tools.