Stanford Researchers Demonstrate Gigahertz-Speed CNT Interconnects

David Lammers, News Editor -- Semiconductor International, 2/16/2008 5:30:00 AM

Researchers at Stanford University (Palo Alto, Calif.) have developed a method of placing multi-walled carbon nanotubes (MW-CNTs) as wires, with gigahertz-level interconnect performance observed for the first time.

H.-S. Philip Wong, the Stanford electrical engineering professor who supervised the work by doctoral student Gael Close, said, “Until now, there has been very little experimental verification of nanotube wiring in a digital circuit, though there has been a lot of anticipation that nanotubes could work as interconnects. This convinces us that using nanotubes for wiring is a promising approach.”

The project also involved several Toshiba Corp. (Tokyo) researchers who designed a ring oscillator test chip to determine the nanotube interconnect performance. The 0.25 µm test chip was fabricated at Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) and then returned to the Stanford Nanofabrication Facility, where the CNTs were connected. The solution of nanotubes was provided by Helix Material Solutions Inc. (Richardson, Texas).

Stanford graduate student Gael Close developed a unique deposition method of placing nanotube interconnects on a test chip.

Details were published Wednesday in NanoLetters. The challenge involved fixing the tubes to a CMOS circuit. Growing the tubes in place was out of the question: nanotube growth requires ~800-900°C temperatures, which would melt a CMOS chip.

To place the tube, Close devised a placement technique that employed the dielectro-phoretic effect. Gold electrodes were created in pairs, and an alternating current (AC) field was created across the two electrodes. A solution containing the CNTs was dropped in place. The ~200 KHz AC field attracted one of the long, thin nanotubes (~5 µm in length and ~50-70 nm in diameter), causing the tube to line up and bridge the two electrodes.

The experiment uses multi-walled carbon nanotubes ~70 nm in diameter and 5 µm in length.

“Once the tube bridges the electrodes, it disturbs the electric field pattern immediately around it, which then no longer attracts any more nanotubes. That is how we have one tube for each electrode pair,” Wong said.

The speed of the nanotube interconnects was tested by building a 11,000-transistor CMOS device with 256 ring oscillators, each with one level of wire missing, and then placing the tube on top of the electrodes. The packaged test chip was wired up to a PCB and tested to show that digital signals can pass through the circuits at gigahertz-level speeds.

Wong said simulations by professors Jim Meindl of the Georgia Institute of Technology (Atlanta) and Krishna Saraswat of Stanford have shown that CNTs theoretically should be capable of terahertz-level interconnect performance. However, Wong said that previous demonstrations have been relatively slow, mainly due to large on-chip capacitances and some off-chip test elements.

“To have a very high frequency signal, you need to have very small capacitance on the chip. With this experiment, everything was on-chip, and we have very small, femtofarad-level capacitances, which is compatible with the speed you are trying to drive to,” Wong said.

The researchers used single CNTs to create one level of wiring on a test chip containing ring oscillators.

While CNTs in very small diameters can be either metallic or semiconducting, the tubes with relatively large diameters used for interconnects are almost always metallic, he said. “It still is hard to control the insulating or metallic properties of the small-diameter nanotubes required for digital switching. For interconnects, it is different. Typically, the bandgap of a nanotube is inversely proportional to the diameter. The larger the diameter, the smaller the bandgap. With the large-diameter tubes, the bandgap is almost zero, which means that it is conducting,” Wong said.

However, the CNT resistance level can be several times higher than copper, requiring more work to improve the purity of the tubes.

An advantage of CNTs is that they are resistant to the electromigration (EM) effects seen in small-diameter copper wires. EM causes copper atoms to move in the opposite direction of the current passing through the wire. If enough copper atoms move out of place, a void is created and the wire fails.

Wong said the main challenge with CNT interconnects is to come up with a set of integrated processes to put the tube on top of the CMOS chip at high yields. “We used a very small chip, only 5 mm on a side, and we have to do 4-5 levels of lithography on top. If we do it on a wafer, that shouldn’t be so much of a problem,” he said.

The Stanford project is being supported with a three-year grant from the MARCO Interconnect Focus Center. Wong said Close is already working to reduce the diameter of the CNT interconnects and improve the yields. In the first experiment, 19 of the 256 CNT interconnects successfully operated, an ~8% rate. Also, the team wants to demonstrate more complex circuits, with more than one wire in the same circuit.