3-D Analysis Progressing to Meet Device Needs

Alexander E. Braun, Senior Editor -- Semiconductor International, 2/12/2008 7:41:00 AM

Although there are several tools and concepts available, the analysis of ultrashallow junctions (USJs) is increasingly becoming an unavoidable problem requiring resolution. “The Holy Grail in this area of metrology is being able to produce a complete 3-D profile — dopant and carrier — for a device,” said Wilfried Vandervorst, head of the Materials and Components Analysis group of IMEC’s (Leuven, Belgium) Process Technology Division. “As planar devices are replaced by 3-D structures, metrology tools capable of probing the dopant or carrier distribution of, for instance, a finFET, become necessary. These should be capable of providing sensitivity, quantification, accuracy, reproducibility and spatial/depth resolution data comparable to today’s 1-D and 2-D tools.”

IMEC has devoted a decade-long effort to 2-D and 3-D analysis using various probe technologies. “Particularly in our 2-D work, our major accomplishment has been breaking the nanometer barrier; we are now down to ~300 picometers in terms of spatial resolution,” Vandervorst said. “This enables us to look at even smaller structures enabling us to see the 3-D dopant distribution inside a transistor, which requires extremely precise measurements to determine the overlap, the effective channel length — basically, the transistor’s heart, wherever the dopants are located.” At the 22 nm node, the dimensions Vandervorst refers to are at the nanometer level. Their importance is out of proportion to their size, requiring extremely high spatial resolutions to be able to measure them with the requisite high precision.

“We’ve accomplished a major improvement by going from measurements in air to measurements in vacuum,” Vandevorst stated, “which solves many problems by allowing measurements to be run at lower probe forces, and providing more reliable results and better space resolution.” While this is a considerable achievement in the 2-D metrology space, the quantum leap being pursued is being able to do this in 3-D for devices such as finFETs. As Vandervorst put it, “With 2-D, you can take a transistor, cross-section it and measure it right there on the cross-section. This works very well. However, when you are dealing with a 3-D device, it becomes impossible to do that kind of measurement. Consider that the gate of a finFET would be 50 nm — how do you cross-section a 50 nm gate?”

Schematic view of a finFET and the 2-D profile requirement in the source/drain region. Source: IMEC.

The illustration shows this 3-D structure and indicates how far the dopants can distribute underneath the gate. “The whole thing is some 10 by 50 nm,” Vandervorst said. “Within those 10 nm, you face extremely difficult space resolution problems and confinement problems because you are getting down to dimensions where the number of atoms is limited, maybe five dopant atoms in one transistor. It is clear that the accurate positioning of junction depths and the measurement of lateral interdiffusion will require very advanced averaging and statistical data analysis to achieve meaningful results. We are developing a system that’ll enable 3-D measurements at an atomic scale. This is an electrical measurement, and there is a counterpart in atom probe measurement where we are counting atoms. For the future, everything comes down to be able to measure extremely small volumes with 3-D space resolution — electrically as well as chemically.”

Although inevitable, going to 3-D using an atom probe is not going to be a simple matter. Yet to be determined are the methodology, physics and the quantification that are needed to make this metrology technology work. IMEC expects to have results in the dopant and atom probe in 1-1.5 years. The researchers are in the process of exploring scanning probe concepts, and expect to have good results within that same time period.