Sematech: High-k/Metal Gate Must Overcome Scalability Hurdles
Alexander E. Braun, Senior Editor -- Semiconductor International, 2/4/2008 8:47:00 AM
First-generation high-k/metal gate is here. However, as the technology moves to the second generation, the industry must overcome several challenges, according to Raj Jammy, director of the front-end processes division at Sematech (Austin, Texas). “Can we scale it without excessively disturbing reliability, performance and other parameters? How well will these first- or second-generation high-k materials, and the electrodes associated with them, work with other performance boosting elements, such as strain engineering?”
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| Raj Jammy, front-end program director, Sematech |
Developers have a good idea about what the issues are with first-generation gate dielectrics and the electrode systems that go with them. “It’s the integration approach that’s in doubt. Shall it be gate first, gate last, or a mix of the two — a hybrid integration approach? It depends how it can be made to work,” Jammy said, adding that there will be proprietary solutions adapted to specific structures used by each company. “Some solutions will be amenable to scaling, while others will work better with performance enhancement factors we haven’t yet thought of.”
At the 45 nm node, the inversion thickness being pursued is in the range of 14 Å, or 1.4-1.6 nm. This is relatively easy to accomplish with metal gates, since dielectric stack thicknesses are not too aggressive. “For the following generation, the expectation is that this will go down by at least 2.0 nm, so we’d be looking at 1.2 nm inversion thicknesses,” Jammy said. “And it’ll have to be attained without additional leakage, charge trapping, mobility problems or lesser performance.”
Most will try the straightforward scaling approaches first, especially for those moving from 45 to 32 nm with the same stack. “Some of us are concerned about what comes in two generations — whether straightforward scaling work will work; otherwise, what are the options?” Jammy said, adding that new materials and new approaches to making the gate stack will require costly development.
A possibility is the use of materials with a higher dielectric constant than the first-generation hafnium-based dielectric materials. Sematech is carefully investigating the interface between the substrate and the high-k dielectric; considerable electrical thickness is lost to that interface, which is still made up of SiO2-based materials. Jammy thinks this should be scaled first, to gain a few angstroms. However, this creates mobility and performance difficulties, requiring careful engineering. “Fortunately, these possibilities fit into existing gate stack structures and models, and may not be too far off from what is used today,” he said. More radical approaches might include reengineering the gate stack, but it is unlikely that something as radical will be done in the near future.
If the industry goes to 3-D devices — likely in a generation or two — that would require reengineering the gate stack, because when devices like finFETs or tri-gates are used the gate must be mapped around the FET, requiring that material properties be identical all around the FET and that the electrodes also behave the same all around the gate. “We’ve done preliminary demonstrations for all such devices and parameters,” Jammy said. “However, overall, it’ll be a challenge, because by then you’ll have to scale the EOT, ensure you have the right metal stacks to swing the Vt, and we’ll have mostly depleted channels, which require that the Vt be controlled from the metal gate.”
Beyond that, the option will be high-mobility channels. At this point the gate stack must be different — especially the interface engineering — because researchers do not quite realize what would be the right gate dielectric material on, for example, germanium, or a VFET device. Possibly III-Vs might be used for high-mobility channels, requiring drastic reengineering.
“More research is needed in high-mobility channel materials,” Jammy said. “We have unresolved issues, such as what kind of a gate stack to come up with that has low defect densities and aggressive EOTs with low leakage.” Some III-V compounds might work; InGaAs, for example. There are many unknowns, such as how to put InGaAs on a silicon wafer, how to grow epitaxial-quality material with appropriate buffer layers on a silicon wafer platform. Then everything must be pulled together — the dielectric and the epi and mobility channels — and junctions must be made. It is yet to be determined if it is possible to engineer more performance, or whether these materials can be isolated without contamination to neighboring devices or materials that affect device properties, he said.
