Industry News

Staff -- Semiconductor International, 2/1/2008

Heterogeneous CMOS Gaining Momentum

Research groups are stepping up efforts in heterogeneous semiconductors as a way of extending CMOS, using epitaxial techniques to deposit materials with higher mobilities than silicon. Heterogeneous devices may be formed on silicon wafers, incorporating, for example, germanium in the pFETs and III-V materials in the nFETs, including GaAs, InGaAs or InSb.

Sematech (Austin, Texas) has quietly increased its heterogeneous device activities, according to Raj Jammy, front-end program manager for the organization. Aixtron Inc. (Sunnyvale, Calif.) and Sematech co-sponsored a workshop on the topic coinciding with the International Electron Devices Meeting (IEDM) in December.

Jammy said he believes heterostructures could replace silicon transistors on perhaps 10% of the devices in a chip in the critical circuits where performance would be limited by silicon transistors. "The idea is not to replace silicon as a starting material. Companies could use [heterogeneous devices] selectively, creating an ultrathin film just in the channel regions, where you want the performance boost to come from. If we use them selectively, we don't have to switch to III-V wafers."

Heterogeneous devices incorporate germanium in the pFETs and III-V materials in the nFETs, including GaAs, InGaAs or InSb. (Source: D.K. Sadana, IBM Research)

The impetus for the research comes as performance gains in silicon become more difficult to come by. Scaling to smaller device dimensions alone doesn't guarantee performance gains. Dimitri Antoniadis, a professor at the Massachusetts Institute of Technology (MIT, Cambridge, Mass.) and director of the multi-university Focus Center for Materials, Structures and Devices (MSD), said that brute scaling of today's silicon devices may result in performance degradation rather than performance gains. His simulations show capacitance, measured at the first-level metal, is increasing and not being compensated by increased velocity of the carriers.

"Basically, the model shows that from 65 to 45 there is some gain but, by the 32 nm node, there may be none, or may even scale in reverse," Antoniadis said. "By that, we mean 32 nm transistor performance may be lower than 45 nm, though we need to update the model on the basis of what Intel and other companies present. Then we may have a better idea."

The challenges with silicon scaling, Antoniadis said, are external resistance at the source and drain regions and an increasing capacitance load for transistors with a dense contacted pitch. Looking only at gate capacitance doesn't provide an accurate picture when parasitic capacitance is becoming a more important factor, he added.

In a presentation at IEDM, MIT professor Jesús del Alamo said the 15 nm generation coming in 2013 "might be the last on silicon. Beyond that, we have to take the advantages of silicon substrates and bring in new materials."

At that point, III-V devices on silicon substrates may compete with transistors incorporating carbon nanotubes and nanowires. Del Alamo said the advantages of III-V nFETs are well-known, including much higher electron transport properties and good reliability. However, III-V materials have bandgaps that "in general, are worse than silicon." Also, the hole mobilities "in general, tend to be worse than silicon."

That is leading researchers at Sematech (Austin, Texas) and elsewhere to examine the advantages of combining III-V-based nFETs and germanium-based pFETs. Germanium transistors excel at hole transport, but are weak in electron mobility.

Jammy, an IBM (Fishkill, N.Y.) assignee to Sematech, said a major challenge is the lattice mismatches that exist between silicon, germanium and the various non-silicon materials. "Dislocations are the big issue, but we have shown we can control that very nicely. In general, we are shooting for something in the low e¹¹ dislocations, and we can demonstrate that now."

Using epitaxial deposition, it may be practical to deposit ultrathin layers of germanium on top of silicon, creating a buffer on which one of the III-V materials could be deposited. Because germanium would be present as a buffer for the nFETs, that would make it easier to create pFETs using germanium as the channel material.

— David Lammers, News Editor

Unexpected nFET Gains for (110) Silicon

The future of CMOS may switch from the (100)-oriented crystalline silicon used throughout the semiconductor industry today to (110)-oriented wafers, according to Sematech (Austin, Texas) researcher Rusty Harris.

Working with Professor Scott Thompson of the University of Florida (Gainesville, Fla.), Harris, an assignee from Advanced Micro Devices (AMD, Sunnyvale, Calif.), studied the performance of pFETs, which normally are faster on (110) wafers, and nFETs, which normally are slower on (110) silicon. However, with an optimized high-k/metal gate technology on the (110)-oriented wafers, Harris found no degradation of the nFETs in velocity saturation mode, while pFETs continued to show the expected 30% performance gain.

The bottom line: a significant 15% improvement in ring oscillator performance for the (110) silicon at no apparent increase in cost or process complexity. The research builds on the development of high-k/metal gate technology over the past few years, solving the nFET mobility degradation and pFET threshold voltage stability issues.

In (110) silicon, PMOS devices are roughly symmetrical to the NMOS transistors.

"Once we fixed the interface states which caused scattering, we found that the transistors scale so that velocity saturation dominates," Harris said in an interview at Sematech following presentation of the research at the International Electron Devices Meeting (IEDM) in Washington, D.C., in December. Thompson had predicted that at smaller device dimensions, velocity saturation, in which drive current no longer increases once a certain level of voltage is achieved, would be the dominant real-world factor limiting nFET performance rather than simple electron mobility or linear drive current.

An initial study was performed in 2006 by S. Krishnan, then a University of Texas at Austin graduate student working as a Sematech intern, who is now an IBM (Fishkill, N.Y.) researcher. Krishnan published that work at the 2006 IEDM.

In 2007, Harris led an effort to fabricate devices with channel lengths of 80 nm, made in a 130 nm process technology. Harris said the result was "symmetric performance for NMOS and PMOS. The curves are nearly identical. That means that we get all the benefits of (110) PMOS without the degradation predicted earlier for NMOS."

Raj Jammy, front-end program manager at Sematech, said electron mobility is degraded in the (110) silicon, compared with (100). However, independent of the lattice orientation, nFET performance depends not on mobility but on velocity saturation. Because there is not a big difference in velocity saturation for either crystalline orientation in the NMOS transistors, the gain in the PMOS transistor performance offers speed benefits at little or no additional complexity, he said.

Jammy said that with higher-performance pFETs, companies would be able to achieve symmetry between the nFETs and pFETs. That would permit smaller pFETs than required today, yielding improvements in transistor density.

Also, the switch to (110) does not appear to impact leakage currents, either gate-induced drain leakage (GIDL) or other causes of leakage. That is important for companies seeking to improve performance while keeping power consumption, and costs, roughly the same.

Harris said the pFET performance is roughly 1 mA/μm, which he said is nearly as good as the pFET presented at IEDM by Intel Corp. (Santa Clara, Calif.) for its 45 nm technology. "Once we've done the right junction engineering, we get symmetric performance of about 1 mA/μm. Intel and TSMC are at about that for their pFETs. And we are very near that without using strain techniques, and with larger gate lengths and an extremely simple flow," Harris said, adding that the improvements "should be more exaggerated as we go to shorter gate lengths."

The interest in (110) silicon has increased in recent years, as IBM and others have studied the possibility of using (110) silicon for the pFETs and (100) silicon for nFETs on the same wafer. That hybrid-orientation technology (HOT) approach usually involves using epitaxial deposition and silicon on insulator (SOI) wafers. The end result of one hybrid approach is to create a (110) SOI device for the pFET and a (100) bulk silicon device for the nFET. However, the process complexity, yield losses and added costs were seen as barriers for most applications.

Harris said Sematech has studied the use of (110) silicon for finFETs and found that the performance gain holds for the vertical devices, which are fabricated on SOI wafers using fully depleted CMOS.

Also, because the openings in the lattice are larger with (110) silicon, the switch to (110) affects the depth of ion implantation in the junctions to the source and drain (S/D) regions. To keep the desired shallow profiles, the Sematech team used well-known germanium roughening techniques to create amorphous silicon in the S/D regions. That improved the dopant profiles.

"We did further studies to understand the impact on the junctions," Harris said. "When we do high-energy implantation, the ions can channel through more easily because the silicon spacing is larger. That caused a slight difference in both junction depth and overlap."

Asked if the chip industry is likely to eventually make a major switch to (110) wafers, Harris said, "We do see this having an impact."

Jammy said Sematech will continue to do the fundamental research this year, as it transfers its accrued knowledge out to the Sematech member companies. "The next step is to try and incorporate it in other devices, which are dimensionally scaled, with different gate stacks. There is potential for next-generation memory work and for high-performance as well."

— David Lammers, News Editor

Nanoimprint Litho Ramps for HDDs, CMOS

Nanoimprint technology will solidly enter the hard disk drive manufacturing arena next year, and find edge-of-the-envelope applications in CMOS high-density memory processes a couple of years after that, according to Mark Melliar-Smith, CEO for Molecular Imprints Inc. (Austin, Texas), a developer and manufacturer of imprint lithography tools.

Melliar-Smith, the former CEO of Sematech, said the complexity of double patterning (DP) lithography will tip some semiconductor industry customers to nanoimprint for certain mask layers. He pointed to Toshiba Corp.'s (Tokyo) early data as proof that the technique will work for makers of leading-edge NAND flash.

However, the approach faces alignment challenges, and critics say the cost of making the reticles will be high. Unlike conventional lithography, with mask patterns that are 4× larger than the printed image, nanoimprint is a 1:1 template technology in which the patterns on the template are impressed in a liquid, which is then cured by ultraviolet (UV) light.

Asked about concerns over 1× technology defectivity problems, Melliar-Smith dismissed them. "In our case, the technology used for the manufacture of 1× imprint masks is based on that used to make phase-shift photomasks," he said. "Our capability to drive down to 1× technology is based on the extension of optical lithography. To extend optical litho to deep subwavelength imaging, the industry has had to use optical proximity correction on their photomasks. Many of those features are smaller than those that are going to be actually printed. So you're already pushing photomask technology well under 4×, as well as in the image placement areas."

IBM has used nanoimprint lithography to print finFET memory devices. The top image shows fins produced using Molecular Imprints’ S-FIL technique, and the bottom image shows a cross-section of the full structure. (Source: IBM)

For DP, CD control is directly related to image placement on the photomask. "This is driving pattern generator companies to push their image placement capabilities to much better levels than those used for 4×," Melliar-Smith said. "Both those factors are allowing the industry to move down to a 1× capability."

Presently, nanoimprint technology is complementary to optical technologies. Molecular Imprints' tool is specifically designed to mix-and-match with 193 nm optical lithography; it is not meant to replace it. Nanoimprint lithography's advantage, Melliar-Smith said, is twofold: It can provide high-resolution, good line edge roughness (LER) and CD uniformity in a simple, inexpensive manner, compared with optical lithography. "With optical lithography, if you want to get below 30 nm, you're not only talking about 193 immersion, but of double patterning. Thus, all of a sudden, what was a simple litho step has now grown into a significant process module involving multiple steps, processing, etching, not to mention design and much more complex overlay and CD control," he said. "Nanoimprint offers very high resolution in a system that is not only simpler in its process, but much more cost-effective. If you compare the cost of imprint tools to that of EUV tools, for instance, we're cheaper by at least a factor of five."

Toshiba has shown impressive nanoimprint data connected to 18 nm feature size work: <1 nm CD uniformity, <2 nm LER, and the chipmaker confirms down to 20 nm overlay for the Molecular Imprints tool. Toshiba began publishing results six months after taking ownership of the tool, an unusually short time.

"This confirms the simplicity and ease of use of imprint lithography," Melliar-Smith said. "Since then, there has been continued progress and improvement on defectivity and overlay, and we're now focused on large markets. In the disk drive and memory industries, there is an enormous advantage and benefit in going to high resolution, which is why the memory roadmaps for lithography are far steeper than those for logic. There's an enormous pull from both those industries to get nanoimprint to manufacturing. If, like Toshiba, you want to be at 20 nm, there are no other options."

An important advantage of nanoimprint lithography is that much of its progress has been built on existing CMOS technology. The process technology is essentially identical to that used in photolithography. This means manufacturers do not have to change any of their upstream or downstream technologies, Melliar-Smith said.

Nanoimprint providers and their users are focusing on the high-density memory — such as NAND flash — area of the CMOS world, and are sparing no effort to meet roadmap demands. "Memory is definitely the sector where we have found the most traction for our technology," Melliar-Smith said. However, he added that although the focus is certainly on high-density memory, it extends beyond just solid-state CMOS memory. "The hard disk drive industry is very important for us, particularly now that they're working at such small dimensions. Their magnetic domains now need more than just magnetic confinement to prevent cross talk."

The CMOS industry expects to benefit from the nanoimprint experience that will result from its use and application by hard disk drive manufacturers. This should give it a fast ramp-up to CMOS, because most of this experience will be directly transferrable to solid-state memory requirements. Nanoimprint is expected to become a factor in hard disk manufacture during 2009, and Melliar-Smith expects it to steeply ramp up into solid-state memory a couple of years after that.

— Alexander Braun, Senior Editor

MIRAI Team Studies Threshold Voltage Variation Causes

With transistor threshold voltage (V_t) variability now a top-shelf concern, a group of researchers, led by Toshiro Hiramoto, at Japan's Millennium Research for Advanced Information (MIRAI, Tokyo) consortium have studied the role of dopant levels and other factors.

The MIRAI team determined that V_t variation of NMOS transistors depends only in part on dopant variations, with the flat-band voltage, the thickness of the inversion layer, sheet charges caused by surface states, fixed charges in the oxide, and dopant pile-up at the interface also contributing.

The Hiramoto team prototyped a 2 million-transistor array in 65 nm technology, divided into 1 million n-channel and 1 million p-channel transistors. After measuring V_t variation, the team concluded that although PMOS transistors show a V_t variation largely caused by impurity fluctuations, the NMOS transistors are impacted by a wider array of factors.

The Hiramoto group prototyped chips with 26 test element groups (TEGs). Each TEG has 20 sub-chips. The arrays were aligned in the same direction. The team evaluated MOS transistor characteristics, including V_t and subthreshold current.

MIRAI researchers studied the role of dopant fluctuations and other factors in threshold voltage variability.

The results showed a Weibull distribution among a total of 100 million tested transistors. The V_t variation data showed a linear change in a Gaussian distribution.

The V_t ranges from +5S (standard deviations) to -5S for NMOS and PMOS transistors. A single variation (1S) of V_t was 43 mV for the p-channel transistors and 65 mV for the n-channel transistors.

To find out the causes of the variations, the team said it concluded that the V_t variation is expressed as a root of (T_ox + 0.8 nm)(V_t + 0.1 V)/LW rather than the conventional root of LW, where L is gate length, and W is gate width. (T_ox + 0.8 nm) indicates the effective gate oxide thickness at an MOS inversion state, and (V_t + 0.1 V) accounts for the addition of the flat-band voltage of the workfunction difference between the gate metal and a semiconductor with a surface potential contribution of 0.1 V, shown in the equation, qNW_dep/C_ox, where W_dep is depletion width and C_ox is gate oxide thickness.

In their experiments, the results differed for PMOS and NMOS transistors. For PMOS transistors, a gradient of the V_t variation is independent of impurity concentrations. The gradient is always constant. For NMOS transistors, however, the gradient increases with higher dopant concentrations and smaller gate lengths. The team is now developing methods to measure the oxide thickness variations and surface roughness, and is creating simulation models to support its work.

— Kenji Tsuda, Asia Contributing Editor