Novel CD-SEM Overlay Method Improves Dual Trench Patterning CDU

Until recently, device scaling in the semiconductor industry has been accomplished by reducing the wavelength and increasing the numerical aperture (NA) of the lithography exposure system. As the industry reaches the limits of immersion lithography, there are several alternative enhancement approaches to extend this lithography technology to the 32 nm technology node.¹ One of these is accumulative double patterning technology (ADPT) lithography, which is based on exposing the wafer twice at the mask level with an intermediate hard mask etch step to accomplish pitch reduction. ADPT has main two approaches: dual line and dual trench patterning (DLP and DTP). A second patterning option, self-aligned double patterning (SADP), uses the spacer technique to double the resolution. A third option called double exposure (DE) uses the same resist to expose twice and complimentary masks set. The best known DE method is called double dipole lithography (DDL), where horizontal and vertical features are split at the mask level and both exposures are done with dipole illumination. All of these methods can be considered alternatives to single-exposure lithography, which allows scaling down beyond the 36 nm node; however, DTP (and DLP) presents some productivity implications.

An additional concern with DTP is the significant critical dimension uniformity (CDU) consequences it brings in contrast to DLP, SADP and DDL. DTP overlay error variations consume the CDU budget by introducing variations in the interlaced pitch population (odd and even pitches). Thus, it can be observed that in addition to across-chip line variations (ACLV), a new domain of across-chip pitch variations (ACPV) also affects the final wafer CDU (Fig. 1).

1. The 2006 International Technology Roadmap for Semiconductors (ITRS) targets a gap (arrow) between even and odd across-chip pitch variations of <1 nm.

However, if overlay is sufficiently controlled, DTP processes can be an option for memory devices back-end-of-line (BEOL) patterning using 32 nm node technology and below. While the reflective properties of the metal layers would challenge the use of non-scanning electron microscope (SEM)-based overlay measurements, the use of SEM as a primary overlay measurement instrument is encouraging. This article offers a novel overlay measurement and correction approach to contain the DTP process imperfections and minimize the effect of ACPV on CDU.

DTP process flow

A simplified DTP process flow (Fig. 2) starts with spaces on the reticle. Exposing these spaces with a pitch of 128 nm will result in trenches on the wafer. After a first etch step through the hard mask, another set of trenches is exposed with a shift of 64 nm during the second exposure, resulting in a design pitch of 64 nm at the wafer level.

2. In DTP, the left and right edges of a line originate from a different exposure step, so overlay error in the second exposure step causes a CD error in the final line/space profile.

In DTP, the left and right edges of a line originate from a different exposure step (contrary to DLP). This implies that an overlay error in the second exposure step of the dual trench approach ends up as a CD error in the final line and space profile.

DTP overlay measurement

It is possible to measure DTP overlay with a CD-SEM in device resolution (e.g., within a memory grid or special CD-SEM overlay grid mark, located in proximity to the main device grid), after final etch (Fig. 3).¹ The overlay in that case is defined as:

3. 32 nm odd and even lines and spaces (pitches) used for overlay extraction.

After final etch, the pattern paradigm of DTP is almost equal to the one of DLP. CD-SEM measurements of the DLP process, performed at ASML (Veldhoven, Netherlands) on our Verity SEM 2 tool and published at SPIE 2007,¹ demonstrated the robustness of in-resolution overlay measurements (Table), which comply with International Technology Roadmap for Semiconductors (ITRS) requirements.

However, CD-SEM measurement of overlay errors after the second hard mask etch (Fig. 2c) prevents the opportunity for lithography rework. It is, therefore, preferred to develop a method to perform a CD-SEM measurement of overlay errors before the second hard mask etch (Fig. 2b). Thus, to measure the DTP overlay in an accurate and repeatable manner using CD-SEM, we designed a trench-within-a-trench alignment SEM mark that could be located between the die scribe lines or in proximity to the device grid across the die. A cross sectional view of the mark is illustrated in Figure 3. During the first hard mask etch, the narrow trench is formed, and during the second lithography step, the wide trench is formed. The overlay error is then calculated by measuring the offset in the trench center lines (center of gravities [CoG] of the two trenches, Fig. 4).

4. This overlay target measures overlay error as the difference in center of gravity (CoG) between two features defined in the first exposure step (after 1st hard mask etch) and second exposure step (before 2nd hard mask etch).

Where the 2nd exposure CoG is the center of the wide trench and 1st exposure CoG is the center of the narrow trench.

To validate the overlay error measurement, CoG measurements of trenches were compared with intentionally introduced overlay errors (trenches created by SEM Monte-Carlo simulation²). A high correlation factor was obtained (0.974) between the induced values and the actual measurements. Further, other recent CoG overlay measurements performed at ASML using a CD-SEM confirmed 0.2 nm overlay measurement precision and complied with the 2006 ITRS requirement (for 1 nm overlay measurement sensitivity with p/t=0.2).

To take full advantage of this trench-within-a-trench SEM mark design, special process consideration needs to take into account properties of the bottom antireflective coating (BARC) material used for the second exposure. After the second exposure, the filling BARC in the first hard mask trench (in the "trench-within-a-trench" overlay mark) makes it invisible to the SEM (SEM signal dynamics are sensitive only to topography). Therefore, a BARC removal technique should be considered after the second exposure. One possible approach, borrowed from the implanter process flow, would be the use of a wet developable organic BARC (e.g., Brewer Science implanter BARC, IMBARC),³ with properly modified imaging and process. A developer could clear the BARC from the first overlay mark hard mask trench during the second exposure resist development and allow SEM measurement of the overlay error between the two trenches. Additional R&D is needed to optimize this approach.

DTP overlay correction

To make overlay corrections, CD-SEM overlay results must be fed into an automated process control (APC) system, such as ASML's GridMapper. This APC technology corrects for scanner and process residuals errors (grid distortions), such as translation, rotation and magnification, as well as magnification and rotation asymmetries. As the DTP process suggests, those errors become critical because of the multiple process steps involved. By sampling five or more locations across the exposure fields, the APC solution can make high-order scan corrections (Fig. 5).

5. GridMapper process control solution corrects overlay errors on a per exposure basis using up to 5th order corrections.4

Conclusions

Intrafield DTP overlay residuals errors can lead to severe device yield consequences, as they directly influence the CDU budget. In cases of overlay excursion, productivity can be enhanced by calculating the overlay errors after the second exposure step. Discovered in time, it would be possible to rework the second exposure and correct for the next iteration. CD-SEM overlay measurements application could become a viable method to correct the grid distortion by feeding the overlay measurements into an APC solution, which would dynamically correct for errors, minimize ACPV and maximize CDU performance.

Acknowledgements

The authors would like to thank the ASML Imaging System Development (ISD) team for help creating this article: Ingrid Janssen, Manager ISD CD analysis; Frank Duray and GertJan Janssen, senior engineering staff members.