DFM: The Changing Semi Landscape

To be sure, many of the traditional technology advances that have enabled Moore's Law-like cost reduction and performance improvements are near their theoretical limits. Chip size, which grew exponentially for decades, is approximately flat and eventually limited by current 6 in. reticles (9 in. reticles are said to lack economic feasibility). Wafer diameter, which grew from 1 to 12 in. over the past three decades, may never increase further for the same reason. Optical lithography appears to be near the end of its life (again), and semiconductor yields in mature factories are near 100% (the theoretical maximum). Critical dimensions, once measured in multiple microns, are now characterized by tens of nanometers and nearing quantum-mechanical limits. It would seem that the semiconductor industry is maturing, leaving less and less "low-hanging fruit" that can be used to fuel growth at the pace prescribed by Moore's Law.

One signal of a maturing industry is the emergence of calls for improvements in design for manufacturing (DFM). The automotive industry is a case in point. At Ford, engineers perform interference checking between vehicle components using an entirely electronic prototyping tool based on virtual reality system technology.² Trends in this direction are clear in the semiconductor industry. In 2006, Lars Liebman of IBM reported on one such software tool concept called the "Lithography Manufacturability Assessor."³ Liebman's paper was one of many addressing the need for an increased use of DFM methodologies for semiconductors.

Much of the recent industry focus on DFM has centered on managing the impact of the increasing complexity of lithography on process and electrical yield. In 2004, it was estimated that there were as many as 60 DFM start-ups looking for venture capital to build electronic design automation (EDA) tools to implement lithography-DFM (LDFM) concepts.⁴ These LDFM tools generally fall into two classes: DFM tools designed to avoid catastrophic yield events (process window "hot spots") and more ambitious tools that capture the lithographic impact on electrical yield considerations like timing closure. In both cases, the goal of such tools is to prevent gaps in design rules from causing yield loss at fabrication.

Increasingly important are tools that can predict the impact of lithographic variation on important electrical characteristics like timing closure. Lithographic manufacturing processes are subject to variation within an expected range. For lithography processes, this includes variation in the nominal exposure dose and focus. Prior to the 65 nm logic node, it was generally expected that what a designer drew would represent what appeared on the wafer, and that traditional design rules would guarantee that the resulting transistors would meet specifications. The introduction of more aggressive illumination strategies needed to resolve patterns that are much smaller than the wavelength of light used to pattern them has made it more difficult to guarantee the exact shape of transistors. Simply put, what you see in the design data is no longer what you get on the wafer. This disconnect between design and manufacturing can result in unexpected variation in electrical performance.

To stay on the Moore's Law curve, designers will increasingly be required to account for systematic manufacturing variations. So, then, one challenge before the industry is to build a software infrastructure to support the flow of both business and technical information across the supply chain from manufacturing to design. To this end, the Silicon Integration Initiative (Si2) has formed the Design for Manufacturability Coalition (DFMC). DFMC is working together with member companies toward an open-standard IT infrastructure that will provide the means for enhanced communication of information across the IC supply chain and against which design and manufacturing applications can be integrated. This will provide a basis for more complete communication of information to improve design and manufacturing cycle times, more effective integration of the entire flow, choice of applications with less difficulty to insert them into the flow, and faster introduction of new design technology and transfer into production.

Many of the traditional technology advances that have enabled Moore's Law are near their theoretical limits. This fact, coupled with the complexity of manufacturing, is making it increasingly necessary to develop new software tools. Those tools must work in the design flow to provide designers with a way to maximize yield (and profit). These trends, including increased reliance on DFM, are to be expected in a maturing industry. New design methodologies that fully leverage manufacturing information will provide fuel for the future growth of the semiconductor industry.