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Meshed Interconnect Approach Reduces Crosstalk

John Baliga, Associate Editor -- Semiconductor International, 3/1/2001

As speeds continue to increase for leading-edge processors and other ICs, the challenge of handling the signals once they leave the package increases as well. The package substrate, with closer and denser conductor spacings, is becoming a place where crosstalk can interfere with IC performance. Researchers from the High Density Electronics Center at the University of Arkansas (Fayetteville) and from Kyocera Corp. (Kyoto, Japan) have developed a meshed interconnect that reduces crosstalk in the same or even less space than the typical stripline approach. Results of their work were presented at this year's Advanced Technical Workshop on High Speed Digital Interconnects, sponsored by IMAPS.

A typical substrate has conductor planes dedicated for power and ground. Other layers contain signal traces, which basically make them stripline waveguides. The interconnected mesh power system (IMPS) has the power and ground contained in two metal layers, but not on separate planes.

Figure 1 illustrates the IMPS construction. One metal layer has conductors running in one direction, and a second layer has conductors running in the orthogonal direction. Vias connect the layers at each crossing point (1a). Two such constructions are built in an interpenetrating, or interdigitated fashion (1b). The blue mesh is the ground mesh, and the red one is the power mesh.


1. The IMPS topology uses two interpenetrating meshes to save space and increase capacitive coupling between power and ground. (Source: University of Arkansas, Kyocera)

Using this power/ground mesh as a starting point, the power and ground conductors are narrowed where necessary to allow signal traces to pass through. Because signal traces are routed within the mesh, only the two metal layers are used. Fewer metal layers results in less material and lower cost. In addition, this means that each signal trace is shielded on all sides by power and ground traces.

Test vehicles were constructed using co-fired ceramic substrates. The metal traces for both vehicles were built on a 10 mil (250 µm) pitch. Passive tests of the power and ground traces showed that the IMPS traces had much higher capacitance, with higher resistance and comparable inductance compared with conventional traces. The higher capacitance occurs because of the closer spacing of power and ground traces, which helps to condition the power better. Measurements of power distribution noise illustrate the reduced noise (Fig. 2), and pulsed signal-line measurements showed crosstalk to be two to three times less for the IMPS package.


2. Power distribution noise is reduced using the IMPS topology. (Source: University of Arkansas, Kyocera)

Kyocera went on to redesign an existing microprocessor package using IMPS. The original package had seven ceramic layers with four power-distribution planes and two signal layers. The IMPS package required only five ceramic layers, with one dedicated ground plane and three IMPS layers. Pulse measurements showed that the IMPS package had half the crosstalk of the original package.

The improved performance and reduction of material each represent an improvement. As interconnect densities continue to grow, it is not sufficient to rely on the properties of new materials to enable the increased density. Design methods must be used to do more than simply route the signals from one point to another. The IMPS design approach is one example of using design to make better use of the available material to enable increased density and performance.

For additional information on assembly and packaging, go to www.semiconductor.net/assembly

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