Will Analysis Costs Diminish the Profitability of Advanced ICs?
William Eslinger, Motorola Semiconductor Products Sector, Austin, Texas -- Semiconductor International, 3/1/2001
 | At a Glance | | |
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Process development vs. debug
Traditional semiconductor analysis supports two broad and very different tasks: process development and production debug. In process development, analysis simply has to provide feedback on typical device structures. The goal is to determine the integrity and uniformity of new processes; therefore, structures of interest are inspected at random or at regular locations across a wafer or lot. SEM or TEM cross-sectional images are particularly useful because they show the visual appearance of features.
In contrast, debug analysis often requires isolation of a specific failing device, which may be one out of a million good devices on the chip. Debug is typically performed on packaged parts after full functional testing. Functional failures of this type may be the result of a mask or design defect, or they may be caused by the combination of geometric layout and marginal process capability (see "Where's Waldo ... and the IC Defect," for an example of a layout-affected, metal etch defect). The major hurdle in debug analysis is fault isolation, which is an electrical needle-in-a-haystack type of search.
The different nature of these two analyses is the reason development analysis is not being affected by recent trends, but debug analysis is. While technology advances are being developed and implemented into fabs as quickly as ever, the ability to debug new circuit designs and achieve mature yields is suffering.
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Recent advances in process technology have hampered debugging efficiency by effectively making two stalwart short-cut analysis methods obsolete. Previously, photo-emission analysis and liquid-crystal techniques allowed analysts to directly locate problem areas by revealing abnormal light or thermal characteristics.
Analysis would then proceed with electrical probing to identify faulty devices and would conclude with either top-down deprocessing or vertical cross-sectioning to find physical evidence of the failing mechanism. These quick-analysis methods are dependent on several capabilities: 1) the ability to view circuitry while functionally exercising it; 2) the ability to detect the emitted levels of light or heat; and 3) the ability to probe component nodes while exercising the circuit.
Unfortunately, the industry's circuit and process technology developments have had an exacerbating effect on the necessary capabilities for such short-cut analysis. These developments (Table 1) include decreases in supply voltages and feature sizes, increases in the number and coverage of metal layers, and system-on-a-chip (SOC) methodology. In fact, flip-chip packaging (typically required for SOC) changes the rules of the game entirely. Correspondingly, traditional short-cut analysis methods fail to address an ever-increasing number of debug analysis jobs.
| Table 1. The Effect of Manufacturing Advances on Analysis | ||
| Manufacturing Advance | Analysis Effect | Analysis/Development/Need |
| New package/circuit materials | Obsoleted deprocessing recipes | New deprocessing recipes and methods |
| Decreases in supply voltage | Diminished light/heat detectability | Greater reliance on slower fault isolation methods |
| Decreases in minimum feature size | Increased difficulty of optical inspection and manual probing | Greater reliance on electron microscopes, FIB-constructed probe pads and e-beam probers |
| Increases in the number and the coverage of metal layers | Diminished light/heat detectability, increased difficulty in FIB navigation, probe access and fault localization | Greater reliance on slower fault isolation methods, CAD navigation, design-for-analysis structures and FIB-constructed probe pads |
| System-on-a-chip methodology | Increased difficulty in exercising circuit blocks | Greater reliance on design-for-analysis structures and test pattern development |
| Flip-chip packaging | Obsoleted current top-side analysis methods | Development of new backside and pre-package analysis methods |
The typical alternative to short-cut analysis involves the tracing of signals in an attempt to identify the fault origin. Signal tracing places a higher premium on the capability of probing nodes while exercising the circuit, but other factors come into play as well. For instance, analysis complexity is a function of the analyst's familiarity with complex circuit blocks, data flow and layout, and access to critical nodes. These factors determine whether analysis cycle time will be reasonable (days), excruciatingly slow (weeks), or infinite (unsolvable). While technical solutions are being developed, the new tools and techniques have tended to be more narrowly focused, expensive and time-consuming than the traditional, generic methods. Ironically, more expensive techniques are linked to slower, less efficient analysis methods. This is especially true when considering backside inspection techniques being developed to address flip-chip packaging technologies.
Slow analysis methods
It is worth noting that the manufacturing advances listed in Table 1 do not equally influence the complexity of IC analysis. If you equate the first five items (new materials, decreasing voltages and feature sizes, increased metal coverage and circuit complexity) to "rough water" for IC analysis, then the final item (flip-chip packaging) can be likened to "going over Niagara Falls." The former requires evolutionary changes in analysis methods, while the latter requires a revolutionary change in the way analysis is done. The answers to the questions in Table 2 can help an analyst determine analysis cycle time.
| Table 2. Checklist for Determining Analysis Efficiency | |
| Indicator Questions for Analysis Cycle Time | Comments |
| How familiar is the analyst with the circuit blocks, the data flow, and the layout of the part? | There is an inevitable learning curve for new designs, along with the physical overhead of creating test boards and test patterns. |
| Does top-level metal provide sufficient access to critical nodes of circuit blocks? Can top-level metal be exposed without changing the characteristics of the failure? | While there may be good manufacturing reasons for extensive metal coverage, it tends to inhibit both quick analysis methods (light and heat detection) and slower analysis methods (node access for signal tracing). |
| How consistent and numerous are the faulty parts? | A more conservative and time-consuming approach is needed with one-of-a-kind failures. |
| Is the fault contained in a circuit with feedback, so that corrupted output results in corrupted input to the same circuit? | This type of feedback condition masks the origin of the fault and increases the difficulty of electrical isolation (circuit example: digital filters). |
| How long is the path between the failing output pin signal and the origin of the failure? | When signal tracing is begun, there is no way of knowing whether the path will be just a few steps or hundreds of steps. |
Analysis considerations
Before discussing possible ways of dealing with the changing capabilities of IC analysis, it's worthwhile to keep in mind an analysis maxim, namely, "In order to be of practical benefit, debug analysis must provide a specific description of the failure cause." Half-answers are as good as no answers.
A circuit designer or manufacturing engineer will not be able to address a situation if told the output of a particular flip-flop is stuck. But he/she can address the problem if told that a particular contact in that flip-flop is floating or poorly formed. Therefore, high-cost analysis tools, which can isolate problems down to a circuit level or device level, are of little value unless the means exists to go from that point to the identification of a specific cause. In a similar manner, a backside mill and probe tool may have the ability to detail a fault in a specific device, but a method must exist to isolate the fault down to that particular device.
Design-for-analysis
There are some commonsense steps — which can be taken up-front — to facilitate the type of feedback needed to correct design/manufacturing problems. These actions fall under the categories of design-for-test (DFT) and design-for-analysis (DFA). They include circuit designs that, to a certain degree, can be analyzed with software (scan-based designs). Another prudent step is to create structures in the chip layout that ensure analysis access to critical probe points. Such steps will narrow the scope of a failure search and thus help shorten the time to isolate a fault. But they do not, by themselves, help you identify the specific mechanism, i.e., provide the useful information needed by designers and process engineers.
New techniques
If analyzing flip-chip products is part of your future, gather a lot of cash and prepare to venture into the world of exotic new backside analysis tools like picosecond imaging circuit analyzers (PICAs) and laser voltage probes (LVPs). The new tools are accompanied by an array of new techniques such as light/thermal-induced voltage alteration (LIVA/TIVA), Seebeck effect imaging (SEI), and optical-beam-induced resistance change (OBIRCH). In backside analysis, techniques tend to become more complex, expensive and time-consuming. What is less certain is whether the new methods will produce the specific information required to fix the design/production problems.
Another approach — which I personally would like to see developed further — parallels the known-good-die (KGD) testing paradigm. In KGD approaches, chips are tested to the fullest extent possible prior to packaging (while still in wafer or die form) to avoid the expense of packaging non-functional chips.
For the purpose of flip-chip analysis, it should be feasible to design for the test and analysis of circuit blocks even before the final metal layers are constructed. If critical circuit blocks could be completed and self-contained after two or three metal layers, normal processing could be halted and a special metal mask used to allow for the testing of critical circuits. Die with malfunctioning circuit blocks could be identified and receive a special top-side package-for-analysis treatment, which would preserve the capability of traditional analysis techniques.
Design and manufacturing personnel may feel the last approach places an unjustifiable burden on their primary goal of profitably designing and creating integrated circuits. Manufacturing personnel may believe analysts are taking this special metal mask approach for the sole purpose of protecting against infrequent events (i.e., yield crashes and non-functioning new designs). The point I wish to emphasize is that without the critical feedback provided by efficient IC analysis, yield crashes and non-functioning designs may not be so infrequent.
Conclusions
While analysis can be considered an insurance policy that provides a means of recovering from disaster, it also serves as a mechanism for refining and perfecting a very complex manufacturing process. IC analysis tools have, thus far, done an admirable job in providing these services to the semiconductor industry, but new approaches will be required to extend that track record.
Strolling through life (or semiconductor manufacturing) without the vision needed to correct your course — and without insurance to recover from disaster — is generally not viewed as a wise choice.
| Where's Waldo ... and the IC Defect-- | ||||||||||||
In this specific case, the red line superimposed on the die (Fig. 2) shows the path followed. The trail started at the fault output pin and proceeded to the cause of the failure — a small area with an unetched bit of metal that caused an electrical short between two lines. Along this path, there were 67 different "forks in the road." Tracing the signals to find the cause of the fault took approximately three weeks.
(Where's Waldo is the copyright of Martin Handford.) | ||||||||||||
Phone: 1-512-933-3420
e-mail: wm.eslinger@ieee.org
