ESH Issues Make Progress
Ron Chiarello, Etalon Technologies -- Semiconductor International, 3/1/2001
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Perhaps the greatest issue facing environment, safety and health (ESH) in the semiconductor industry is the integration of ESH technology and manufacturing. ESH technology can be seen as having two major components: 1) the management and control of any human or ecological hazards that may be associated with manufacturing; and 2) assistance with designing environmentally and biologically benign manufacturing processes.1 Figure 1 summarizes ESH and manufacturing integration as described in the International Technology Roadmap for Semiconductors (ITRS). For all of the technology needs, potential solutions to ESH considerations involve processes and equipment optimization, along with the need to find alternative environmentally benign chemicals, materials and processes. At the heart of ESH technology management is the impact and load new chemicals and materials and their byproducts have on the environment; risk assessment; the rapid insertion of ESH information into process development; equipment design; the selection of chemicals and materials; and treatment options of emissions and waste. Resource conservation focuses on reducing consumables and minimizing waste, with an emphasis on reducing ultrapure water (UPW) and energy consumption. The use and emission of perfluorocompounds (PFCs) are prevalent in semiconductor manufacturing and problematic from an environmental standpoint because of these substances' global warming potential (GWP). Global climate change mitigation involves the reduction of GWP chemical emissions through replacement and abatement of PFCs. ESH design and measurement is needed to evaluate and quantify the ESH impact of chemicals, materials and process equipment, and to help make ESH a design parameter in development procedures for new equipment and new processes.
Significant progress has been made in these areas over the past several years, in part because of collaborative R&D between chipmakers, suppliers and universities that make use of ESH technology, and the implementation of optimized processes that help fabs simultaneously realize gains in cost savings, capacity increases and environmental benefit.
Reducing water consumption
Reduction of UPW use is a critical challenge for IC manufacturers. Increasing demand for high-performance integrated circuits has lead to more-complex device architectures, high packing densities, large die sizes and larger wafers, resulting in the need for larger volumes of chemicals and UPW. The cost of obtaining water, the construction and maintenance of large-scale deionization plants, and the treatment and disposal of wastewaters are starting to add significantly to overall manufacturing costs. Some cost-of-ownership models show that the relative cost of UPW for 300 mm wafers will triple compared with other factors.2 In addition, new fabs are being constructed around the world in regions with sensitivities to water supply. In response to theses issues, the ITRS calls for reduction in water use of 62% (to 2.9 L/cm2of silicon) by 2005 and 84% (to 1.2 L/cm2 of silicon) by 2014. These goals must be reached at a time when silicon use will grow at an annual rate of 10.3%.3 A transparent solution for these concerns is to reduce water consumption, thereby lowering both fixed and operating costs and putting less strain on natural resources.4-6 A program sponsored by International SEMATECH helps fabs reduce point-of-use UPW consumption by the optimization of aqueous processes in process equipment.4 The great success of this program is that, in addition to reducing UPW consumption, optimized rinse processes also provide shorter process times, higher tool use and higher wafer throughputs — all of which lead to a lower cost of ownership.
In FEOL surface preparation, UPW is used in cleaning and rinsing steps needed
to provide the necessary wafer-surface quality and to isolate each process step
from the others. Rinse-process optimizations must be based on information about
UPW used by process equipment, and the relationship between the type and
concentration of contamination in rinse waters and wafer-surface contamination
and defects. This information is acquired from detailed in situ measurements of
rinse waters made during wafer processing and ex situ measurements of
wafer-surface quality. Engineers then can use this data to decide between a set
of discrete choices, which can be justified, based on gains in cost savings and
cost avoidance, process-equipment performance and environmental benefits.
Figure 2 shows an example of UPW use for three rinse processes evaluated in an immersion wet bench for rinsing after SC1, SC2 and SPM chemicals commonly used in FEOL surface preparation. The standard rinse recipe used a six-cycle overflow dump rinse (OFDR) with cascade flows. The drain time between OFDR cycles was 3 sec. Optimized rinse strategy number one was a quick dump rinse (QDR) with no cascade flows. The drain time between QDR cycles was increased from 3 sec for the standard rinse to 10 sec for the optimized QDR. Optimized rinse number two is referred to as WASH (water-saving shower).5 This rinse used a high-pressure UPW spray and a single QDR cycle for wafer rinsing. The standard post-rinse process consumed 411 L of UPW and required 8 min to complete compared with 108 L and 2.6 min for the QDR and 54 L and 1.3 min for the WASH. Detailed measurements of wafer-surface quality and rinse-water contamination revealed no differences in performance for the three processes shown in Fig. 2. The QDR process was put into production in one fab and led to >50% reduction in UPW use and an overall fab throughput increase of 3%. Rinse-optimization technology has been implemented in many fabs worldwide, resulting in UPW savings of 25-70%; rinse-time reductions of 25-60%; increases in process equipment wafer throughput of 28-128%; and annual cost savings and cost avoidance of $250,000 to $8M per fab.
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Minimizing PFC emissions
Gases such as fully fluorinated alkanes — CF4, C2F6, C3F8 — as well as inorganic compounds like NF3 and SF6, collectively termed as PFCs, are used by the semiconductor industry for the etching of dielectric films in wafer patterning and plasma-enhanced chemical vapor deposition (PECVD) chamber-cleaning applications. Their use and emission is problematic from an environmental standpoint because PFCs have been implicated as anthropogenic contributors to global warming and long-term global climate change. Although the semiconductor industry's use of these chemicals contributes <0.1% of all greenhouse emissions in the United States, the World Semiconductor Council has a stated goal of a 10% absolute PFC emissions reduction by 2010 from the 1995 baseline levels.
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Some IC makers have demonstrated improved performance and reduced emissions by optimizing etch processes in existing process equipment. This optimization has lead to emissions reductions up to 50% with no impact on process performance. PFCs from etch processes originate from incomplete use of the etch gas and the formation of CF4. Researchers at the CEBSM are developing a novel approach for replacing PFCs in etch using 2H-heptfluoropropane in a high-density plasma process. Results show an 80% reduction in PFC emissions compared with C3F8 having highly similar process performance.
Solventless lithography
R&D being led by Karen Gleason (Massachusetts Institute of Technology) and Chris Ober (Cornell University) at the CEBSM is focusing on development of revolutionary processes for patterning ICs that result in reduced solvent use and also enhance performance for defining smaller IC features. This research could impact the technology of future lithographic generations. One goal is to demonstrate a solventless lithography process that is compatible with advanced exposure tools. A second goal is to combine the functionality of photosensitive resists and low-dielectric constant interconnect materials. Such a directly patternable dielectric layer would greatly reduce the number of processing steps for IC manufacturing, as favored by both economic and environmental driving forces. Finally, integration of these new processes and materials into manufacturing is the ultimate motivation.
Currently, wet chemistry is used both for photoresist application and development. CVD processes and the use of supercritical CO2 as developer may provide critical alternatives to the present solvent-based approaches. Supercritical CO2 has attractive ESH properties, including non-toxicity, non-flammability and low cost. Current manufacturing uses a polymeric photoresist to pattern dielectric layers, such as SiO2. Because of their lower dielectric constant, polymers have been proposed to replace SiO2 in ICs. If deposition of a photosensitive dielectric could be achieved, it would greatly simplify the process flow for microelectronics fabrication. In addition, supercritical CO2 has no surface tension and low viscosity, enabling sub-100 nm feature development without pattern collapse (Fig. 3). Incorporating the beneficial properties of this developer presents multiple opportunities for achieving improvement in patterning.
All dry-resist processing would greatly reduce ESH risks and costs associated with liquid organic waste and volatile organic air emissions. Targeted dry-resist materials include fluoropolymers and organosilicones because of their solubility in CO2, low dielectric constants and photosensitivity at short optical wavelengths. Fluoropolymers are especially attractive for 157 nm lithography.
Both the ITRS and Electronics Industry Environmental Roadmap have identified reduction or elimination of waste associated with photolithography. Photoimageable dielectrics are another high priority on these roadmaps because such materials would greatly reduce the number of manufacturing steps, resulting in less materials usage, energy consumption, waste disposal and overall cost.
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Over the past several years, the semiconductor industry has realized significant gains in reducing consumption of resources and minimizing waste and emissions. This success is due, in part, to international cooperation and collaborative R&D between IC makers, suppliers and universities. At a time when 300 mm wafer fabs are under construction and new chemicals, materials, processes and process equipment are being introduced, ESH considerations should be integrated with manufacturing innovations. ESH technology can then become a valuable design parameter that not only reduces environmental impact, but makes significant contributions to reducing manufacturing costs and increasing productivity. The positive impact of ESH technologies has already been proven to help fabs worldwide realize significant gains in cost savings and capacity increases, as well as environmental benefit. •
REFERENCES
- Bob Duffin, "Future ESH Trends in the Semiconductor Industry," Future Fab International, Issue 8, 2000.
- S. Bhat, B. van Eck, V. Menon, Microcontamination 92 Proceedings, Cannon Communications, Santa Monica, p. 588 (1992).
- Dataquest, SEMICON West forum, July 12, 2000.
- Ron Chiarello, Russ Parker and Mike Tritapoe, "Optimizing wafer rinse processes to conserve DI water," Micro Magazine, June 2000, p. 111.
- R. Parker, R. Chiarello and D. Gomez, Semiconductor Pure Water and Chemicals Conference Proceedings, Santa Clara, March 1998, p. 323.
- R. Hall, J. Rosato, P. Lindquist, T. Jarvis, T. Parry, and R. Walters, "Improving Rinse Efficiency with Automated Cleaning Tools," Semiconductor International, Nov. 1996, p. 151.
- Walter Worth, "Reducing PFC Emissions: A Technology Update," Future Fab International, Issue 9, 2000, p. 57.
