Heterogeneous CMOS Gaining Momentum
David Lammers, News Editor -- Semiconductor International, 1/10/2008 8:09:00 AM
Research groups are stepping up efforts in heterogeneous semiconductors as a way of extending CMOS, using epitaxial techniques to deposit materials with higher mobilities than silicon.
Heterogeneous devices may be formed on silicon wafers, incorporating, for example, germanium in the pFETs and III-V materials in the nFETs, including GaAs, InGaAs or InSb.
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| Raj Jammy, front end program manager, Sematech |
Jammy said he believes heterostructures could replace silicon transistors on perhaps 10% of the devices in a chip, in the critical circuits where performance would be limited by silicon transistors. “The idea is not to replace silicon as a starting material. Companies could use [heterogeneous devices] selectively, creating an ultrathin film just in the channel regions, where you want the performance boost to come from. If we use them selectively, we don’t have to switch to III-V wafers.”
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| Aixtron deposition systems are targeted to compound semiconductors. |
The impetus for the research comes as performance gains in silicon become more difficult to come by. Scaling to smaller device dimensions alone doesn’t guarantee performance gains. Dimitri Antoniadis, a professor at the Massachusetts Institute of Technology (MIT) and director of the multi-university Focus Center for Materials, Structures and Devices (MSD), said that brute scaling of today’s silicon devices may result in performance degradation, rather than performance gains. His simulations show capacitance, measured at the first-level metal, is increasing and is not being compensated by increased velocity of the carriers.
“Basically, the model shows that from 65 to 45 there is some gain, but by the 32 nm node there may be none, or may even scale in reverse,” Antoniadis said. “By that we mean 32 nm transistor performance may be lower than 45 nm, though we need to update the model on the basis of what Intel and other companies present. Then we may have a better idea.”
The challenges with silicon scaling, Antoniadis said, are external resistance at the source and drain regions, and an increasing capacitance load for transistors with a dense contacted pitch. Looking only at gate capacitance doesn’t provide an accurate picture when parasitic capacitance is becoming a more important factor, he added.
In a presentation at an IEDM Sunday short course, MIT professor Jesús del Alamo said the 15 nm generation coming in 2013 “might be the last on silicon. Beyond that, we have to take the advantages of silicon substrates and bring in new materials.”
At that point, III-V devices on silicon substrates may compete with transistors incorporating carbon nanotubes and nanowires. Del Alamo said the advantages of III-V nFETs are well known, including much higher electron transport properties and good reliability. However, III-V materials have bandgaps that “in general, are worse than silicon.” Also, the hole mobilities “in general, tend to be worse than silicon.”
That is leading researchers at Sematech and elsewhere to examine the advantages of combining III-V-based nFETs and germanium-based pFETs. Germanium transistors excel at hole transport, but are weak in electron mobility.
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| This heterojunction device was presented by D.K. Sadana at a 2005 Sematech meeting. |
Jammy, an IBM assignee to Sematech, said a major challenge is the lattice mismatches that exist between silicon, germanium and the various non-silicon materials. “Dislocations are the big issue, but we have shown we can control that very nicely. In general, we are shooting for something in the low E11 dislocations, and we can demonstrate that now.”
Using epitaxial deposition, it may be practical to deposit ultrathin layers of germanium on top of silicon, creating a buffer on which one of the III-V materials could be deposited. Since germanium would be present as a buffer for the nFETs, that would make it easier to create pFETs using germanium as the channel material.
Maintaining the benefits of strain is another important question. At IEDM, Sagar Suthram, a graduate student at the University of Florida (Gainesville, Fla.), presented work he participated in as part of a Sematech project on germanium channel pFETs. In the past, germanium channels required relatively thick graded silicon-germanium buffer layers between the silicon substrate and the thin germanium channel. However, the Sematech project showed that ultrathin germanium layers can be deposited on silicon without strain relaxation.
A second important research challenge is identifying the high-k dielectrics for germanium and III-V-based devices. Matthias Passlack, a research manager at Freescale Semiconductor Inc’s Tempe, Ariz., laboratory, has claimed significant progress in creating a dielectric deposition process for GaAs-based transistors.
Jammy said epitaxial deposition, and creating dielectrics with relatively low defect rates at the interfacial layers, present unique challenges to the equipment industry. “Would we have to integrate the dielectric with the epitaxial system, or do it separately?” he asked.
A few groups are reporting more conventional approaches, using metal-organic chemical vapor deposition (MOCVD) techniques as opposed to molecular beam epitaxy (MBE) with high vacuum requirements. “Whether the industry can used MOCVD or pseudo ALD-type techniques to put the dielectrics on top — all that remains to be worked out,” Jammy said.
Significant challenges remain in figuring out how to form the devices. Forming contacts with heterogeneous devices is a major research area, with direct Schottky-type contacts as one possibility. The critical arena of adding dopants is another. “The dopants are well known in silicon, but their behavior is not that well known in III-Vs,” Jammy said.
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