Industry News

Intel Takes 45 nm High-k/Metal Gate Process to IEDM

Processors on an Intel 45 nm hafnium-based high-k metal gate ‘Penryn’ wafer. The processors incorporate 820 million transistors on each quad core chip.

Kaizad Mistry, vice president of logic integration, said Intel used a "high-k-first, metal gate-last" approach. By keeping the high-temperature annealing steps used to activate the dopants in between the dielectric and metal gate deposition steps, Intel is able to maintain a good workfunction metric for the electrode of its pFET transistor, which he said was 51% faster than the previous generation.

The hafnium-based gate dielectric has a 1 nm equivalent oxide thickness (EOT) for both n- and p-type transistors, with a 7 Å interfacial layer, which Mistry referred to as a "transition layer." Although Intel does not provide its inversion thickness, Mistry said in an interview that the difference between the EOT and T_inv "is about 4 Å, plus or minus 1." The physical thickness of the high-k layer was 18–20 Å, which is thick enough to provide what Mistry said was a 25× improvement in NMOS leakage current, compared with SiO₂, and a three orders of magnitude (1000×) improvement in PMOS leakage.

The 35 nm gate length transistor has an nFET drive current of 1.36 mA/μm at 1 V operation, which he said was a 12% improvement over the 65 nm process. By increasing the level of germanium in the embedded silicon germanium (eSiGe) stressors from 17% at the 90 nm generation to 23% at 65 nm to 30% at 45 nm, Intel has boosted pFET performance considerably, with a 3× improvement in hole mobilities. That results in a 1.07 mA/μm drive current for the pFET, which Mistry said is "by far, the highest performing PMOS transistor." Compared with the 65 nm pFET, the 45 nm pFET is 51% faster.

The stronger pFET is causing Intel's design teams to consider the mix of NOR gates, which rely on the nFETs, and NAND gates, which are more pFET-dependent. "With a higher beta ratio [between n- and pFET performance] of 1.3, we can tell our designers up front so they can take advantage," he said.

For a gate with a fanout of two, the switching speed is 5.1 psec.

In a post-session interview, Mistry said the metal gate-last approach produces a better pFET technology than the gate-first approach. "There has never been a high-performance pFET produced with a gate-first approach." The use of a metal gate helps improve threshold voltage pinning and gets rid of the poly depletion problem that had robbed performance. With an oxide poly gate stack, "We were running out of atoms," Mistry said, making the move to high-k/metal gate imperative.

The major challenge in development of the high-k/metal gate technology was determining a combination of metals that could replace polysilicon in the pFET, one that would provide the proper workfunction.

Scott Thompson, a professor at the University of Florida (Gainesville, Fla.), said he believes Intel is using a mixture of well-known metals, including titanium, titanium nitride, aluminum and tantalum nitride. "It is difficult to know for sure what sequence Intel deposits the metals because, during the thermal cycles, they become intermixed. And perhaps the exact metals are not so important as is the fact that Intel used well-known standard metals. What is important is the process control margins, the rate of deposition and polishing. To keep the level of polishing uniform, within a couple of hundred angstroms, over a 12 in. wafer, over all kinds of topographies, that is an impressive accomplishment," Thompson said.

— David Lammers, News Editor

IBM Alliance Develops 32 nm High-k/Metal Gate SRAM

IBM Corp. (Armonk, N.Y.) has developed a test SRAM array using 32 nm high-k/metal gate process technology, an achievement that puts IBM and its Fishkill alliance development partners on track to introduce 32 nm technology in the second half of 2009.

Pictured (left to right): Craig Lage, project leader, Freescale Semiconductor; An Steegen, project manager, 32 nm bulk technology, IBM; John Pellerin, project leader, AMD; Ja-Hum Ku, project leader, Samsung; John Sudijono, project leader, Chartered Semiconductor Manufacturing Co.; Mukesh Khare, project manager, high-k/metal gate technology, IBM; Richard Lindsay, project leader, Infineon Technologies; Effendi Leobandung, project manager, 32 nm SOI technology, IBM.

Gary Patton, vice president of IBM's Semiconductor Research and Development Center in Fishkill, N.Y., said high-k/metal gate technology will become available not only to the Fishkill alliance development partners, but also to fabless design teams that use one of the alliance partners to foundry their 32 nm designs. IBM plans to accelerate introduction of the 32 nm process, making it available to its foundry partners within a quarter of IBM's own schedule.

"Both Intel and IBM have talked about using high-k 45 nm technology to produce their own parts," Patton said. "What is significant about this announcement is that, through the partners and foundries, 32 nm high-k technology becomes available to the wider industry for the first time. Design teams can start the whole design planning process now."

The 32 nm project team fabricated the 1.5 MB array very recently, with first-pass success, said An Steegan, the 32 nm bulk CMOS project manager. The cell size was described as <0.15 μm², half the cell size of the 45 nm SRAM cell size.

"Variability improves because of the use of high-k," Steegan said. With the scaled oxides, the gate dielectric was so thin that leakage and variability issues were troublesome. "The use of high-k means that in terms of variability, we do not have too many more worries at this stage."

Patton said IBM will use the 1.5 MB array very early in development, progressing quickly to a larger array.

IBM and Advanced Micro Devices (AMD, Sunnyvale, Calif.) are separately developing a silicon on insulator (SOI) 32 nm technology, based on the high-k/metal gate gate-first solution for the 45 nm generation. Patton said IBM will use the SOI 45 nm process for IBM's proprietary products, and will offer a non-high-k 45 nm process to its foundry and OEM customers.

The bulk 32 nm development partners include AMD, Chartered Semiconductor Manufacturing Ltd. (Singapore), Freescale Semiconductor Inc. (Austin, Texas), Infineon Technologies (Munich), Samsung Electronics Corp. (Seoul, South Korea), and STMicroelectronics (Geneva).

The low-power process will be introduced first, using a 1 V operating voltage, followed by more leaky, higher-performing transistors. The 32 nm high-k/metal gate transistors deliver a 45% total power savings and up to a 30% higher performance compared with the previous generation. "Performance absolutely is improving — there is no question in our minds about that. We use a range of benchmarks to measure performance at each technology node," Patton said, adding that PDAs and cell phones require higher densities and faster chips, as well as lower power. "With high-k/metal gate, there is no question they will be able to get much better performance, in part because of the higher density."

Mukesh Khare, project manager of high-k/metal gate technology at IBM, said the gate-first process will make it easier for customers to move to 32 nm. "We focused on the materials aspect so we could insert high-k/metal gate into a conventional flow," he said. "We sought to use materials capable of withstanding conventional high-temperature processing. That supports an ease of integration, with no additional design restrictions, which opens it up to partners and fabless companies."

— David Lammers, News Editor

TSMC Unveils 45 nm HP Process at IEDM

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) came to the International Electron Devices Meeting (IEDM) with a presentation on its 45 nm high-performance process, which moves into early production next May.

With a growing band of companies — including cell phone, graphics and field-programmable gate array (FPGA) IC vendors — pushing TSMC to higher performance levels, the company's technology attracted close attention at the IEDM meeting.

While the TSMC 45 nm process eschews high-k/metal gate technology, it uses "the most aggressive design rules in the industry," said C.C. Wu, deputy director of logic technology development at TSMC. It achieves a poly contact pitch of 162 nm, nearly the same as the 160 nm pitch reported by Intel Corp. (Santa Clara, Calif.). With immersion lithography driving such aggressive design rules, Wu said TSMC engineers worked hard on overlay control, which he said is "very important to have good yields." The 45 nm process yields a gate density that is 2.43× higher than that of the 65 nm process. The gate length is 30 nm, and the SRAM cell size is 0.242 μm².

TSMC adopted embedded silicon germanium (eSiGe) in the PMOS transistors, striving to achieve good SiGe proximity to the channel and moving to a higher annealing temperature.

TSMC added embedded silicon germanium (eSiGe) at the PMOS side to improve hole mobility in its 45 nm technology.

To reduce overall capacitance, TSMC used an interconnect dielectric with a k value of 2.55 from the top metal layer down to the first metal (M1) layer. Because delays from increased wiring capacitance are increasing with each generation, Wu said to achieve a 20% overall performance gain, the transistor front end must be improved by 35–40% with each generation to compensate for the slower back-end-of-line (BEOL).

TSMC used an oxide poly gate stack with a 12.5 Å equivalent oxide thickness (EOT) rather than the high-k/metal gate approach. However, polysilicon depletion adds as much as 6 Å to the gate oxide thickness. Wu said TSMC's evaluation is that device leakage continues to be dominated by subthreshold leakage rather than gate leakage.

Carlos Diaz, director of logic research and development at TSMC, said, "When you look at power vs. speed, the performance delta [between the high-k/metal gate and oxide poly gate stacks] is not that large. It depends on the application. And when it comes to cost, we want to stay on the conventional curve."

Y.J. Mii, the 45 nm program manager, said, "High-k does provide some advantage in terms of performance. From our estimation, high-k provides about a 10% performance gain," but at the impact of additional cost and process complexity.

— David Lammers, News Editor

IMEC Reports Progress on High-k/Metal Gates

Ring oscillator realized with Hf-based high-k dielectrics and TaC metal gates provide a single-dielectric, single-metal deposition approach for the 32 nm node.

A major challenge in using high-k dielectrics for CMOS devices is the high V_t, resulting in low performance. Dual metal gates in combination with dual dielectrics can solve this problem, but have the drawback of much higher cost. IMEC developed a simpler, lower-cost integration scheme using only one dielectric stack and one metal.

While early approaches to high-k/metal gate aimed at identifying the metal with the proper WF to deliver appropriate Vt for the pFET and nFET devices, more recently researchers have discovered the ability to modulate the WF of the device by capping the hafnium-based dielectric (HfO₂ or HfSiON) with more electronegative or electropositive layers, then annealing to shift the WF to the conduction or valence band edge. The IMEC researchers used both a lanthanium- (La₂O₃) and dysprosium-based (Dy₂O₃) capping layer for the nFET and an aluminum-based capping layer for PMOS. To achieve two metals in one deposition step (TaC_x for nFET and TaC_xN_y for pFET), an RF plasma nitridation step was proposed. In this way, physical vapor deposition (PVD) can be used to achieve chemical vapor deposition (CVD)-like concentrations of nitrogen in the film (~8%).

Because thin gate dielectrics suffer from soft breakdown before the specified lifetime and the failure is difficult to forecast, IMEC developed a time-dependent dielectric breakdown model to completely predict the reliability of the devices. The model is based on the statistical analysis of hard breakdown, including multiple soft breakdown and wear out. By applying the model on the high-k/metal gate devices, the excellent quality of the gate dielectrics has been demonstrated.

In strong collaboration with NXP (Eindhoven, Netherlands) and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan), excellent performance (drive current of 950 μA/µm and I_off of 50 nA/μm at V_dd of 1 V for NMOS finFETs) and short-channel effect control were achieved for tall, narrow finFETs without mobility enhancement. PVD of titanium nitride (TiN) electrodes on hafnium oxide (HfO₂) dielectrics gave improved NMOS performance compared with ALD TiN. IMEC also applied the dysprosium-based capping process on finFETs, resulting in a possible candidate technology for 22 nm.

These results were obtained in collaboration with IMEC's sub-32 nm CMOS core partners, including Infineon, Qimonda, Intel, Micron, NXP, Panasonic, Samsung, STMicroelectronics, Texas Instruments and TSMC, and key CMOS partners, Elpida and Hynix.

— Laura Peters, Lead Technical Editor