IMEC Reports Progress on High-k/Metal Gates
Laura Peters, Lead Technical Editor -- Semiconductor International, 12/11/2007 9:11:00 AM
At IEEE’s International Electron Devices Meeting (IEDM), held this week in Washington, D.C., IMEC (Leuven, Belgium) reported significant progress in improving the performance of planar CMOS using hafnium-based high-k dielectrics and tantalum carbide metal gates targeting the 32 nm node. Low threshold voltage (Vt) and conduction and valence band-edge effective workfunctions (WFs) are achieved using thin dielectric caps between the gate dielectric and metal gate. In addition, the use of laser-only annealing for gate stack engineering resulted in a significant reduction of the minimum sustainable gate length and improved short-channel effect control. The same processes were applied on finFETs and resulted in a possible candidate technology for the 22 nm node.
A major challenge in using high-k dielectrics for CMOS devices is the high Vt, resulting in low performance. Dual metal gates in combination with dual dielectrics can solve this problem, but have the drawback of much higher cost. IMEC developed a simpler, lower-cost integration scheme using only one dielectric stack and one metal.
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| 1. Ring oscillator realized with Hf-based high-k dielectrics and TaC metal gates provide a single-dielectric, single metal deposition approach for the 32 nm node. |
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| 2. Ion/Ioff performance for high-k/metal gate CMOS. |
Symmetric low Vt of ±0.25V were achieved, and drive currents of 1035 and 505 µA/µm for NMOS and PMOS, respectively, at Vdd of 1.1 V and Ioff of 100 nA/µm. Successful CMOS integration was illustrated by a ring oscillator delay of <15 psec (Figs. 1-3). Laser annealing, rather than a spike anneal, delivered lower effective oxide thickness (EOT) and better activation on the shallow junctions.
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| 3. Ring oscillator performance realized in high-k/metal gate CMOS. |
Because thin gate dielectrics suffer from soft breakdown before the specified lifetime and the failure is difficult to forecast, IMEC developed a time-dependent dielectric breakdown (TDDB) model to completely predict the reliability of the devices. The model is based on the statistical analysis of hard breakdown, including multiple soft breakdown and wear out. By applying the model on the high-k/metal gate devices, the excellent quality of the gate dielectrics has been demonstrated.
In strong collaboration with NXP (Eindhoven, Netherlands) and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan), excellent performance (drive current of 950 µA/µm and Ioff of 50 nA/µm at Vdd of 1 V for NMOS finFETs) and short-channel effect control were achieved for tall, narrow finFETs without mobility enhancement. PVD and atomic layer deposition (ALD) were compared for metal deposition. Because PVD metals are denser and less porous, PVD of titanium nitride (TiN) electrodes on hafnium oxide (HfO2) dielectrics gave improved NMOS performance compared with ALD TiN. IMEC also applied the dysprosium-based (Dy2O3) capping process on finFETs, resulting in a possible candidate technology for 22 nm.
These results were obtained in collaboration with IMEC’s sub-32 nm CMOS core partners, including Infineon, Qimonda, Intel, Micron, NXP, Panasonic, Samsung, STMicroelectronics, Texas Instruments and TSMC, and key CMOS partners, Elpida and Hynix.
