Gartner: 2008 Semi Outlook Is Softening

Alexander E. Braun, Senior Editor -- Semiconductor International, 12/6/2007 6:43:00 AM

If a recession spares the United States, the semiconductor market should do well next year; however, regardless of the economy, the industry faces fundamental changes. At the Gartner Dataquest Semiconductor Industry Update: Strategic Issues for a Changing Business Environment, held in San Jose, analysts of the information technology (IT) research and advisory company forecasted the industry’s direction over the next few years. Bryan Lewis, research vice president, presented the Worldwide Semiconductor Forecast. According to him, 32 nm-based chips increased design and manufacturing costs will force many companies to redefine how they do business. “Alliances will feature heavily in maintaining competiveness during the 32 nm rollout.”

The 2008 outlook is softening. Increasingly, macroeconomic issues are impacting semiconductor consumption. While the semiconductor market should grow at a 4.8% compound annual growth rate (CAGR) from 2006 to 2011, vendors should be cautious about adding manufacturing capacity during 2008. Gartner views holiday season sales of electronic goods and semiconductor channel inventories carried forward into 1Q08 as a recession weathervane. “Executives should prepare alternate business plans and budgets in case demand weakens if the U.S. slips into recession,” Lewis said.

Based on growth aided by the DRAM market’s cyclical recovery, Gartner revised upward its 2009 growth forecast from 6.1% to 8.5%. A memory oversupply may reduce 2008 growth. Application-specific standard products (ASSPs) make up the largest market, and solid growth is forecasted for these in 2008. ASSPs are not as cyclical as DRAM and NAND flash, and their use is not limited to a few applications. “We revised our market growth forecast for 2008 from 8.2% to 6.2% specifically because of a contraction in the DRAM market,” Lewis said. A slowdown in global gross domestic product (GDP) growth could cause widespread demand-side weakness, pushing market growth further toward 0% growth. Despite lower total growth in 2010 and 2011 (the result of a DRAM and NAND flash memory downcycle), the five-year CAGR forecast remains at 4.8%.

The ASIC market forecast was revised downward from 8.6% to 4.6% because of loss of share to ASSPs in digital cellular handsets and a less favorable video game console product mix. ASSP 2007 market growth was revised slightly upward from 3.6% to 4.3% to reflect a continued shift from ASIC to ASSP in the digital cellular handset market and an increased demand from consumer electronics.

The DRAM market is expected to decline by 5.5% in 2007, compared with a previously forecasted decline of 1.4%; the 2008 growth forecast was revised downward to -16.7% because of an expected oversupply. Although healthy, NAND flash market growth in 2007 is weaker than previously forecasted. That forecast was reduced to 16.6% compared with 24.4% in last quarter’s update; however, for 2008, in contrast to DRAM, an annual growth rate of 28.8% is expected. Lewis thinks memory suppliers will reduce capex spending in 2008. “Recession fears are causing many to readjust planned expenditures,” he said.

While Gartner did not factor a U.S. recession into its forecast, it considered its possible impact. “Based on a rising possibility for a recession in 2008, we advise contingency planning,” Lewis said. According to Gartner, a recession would slow sales of electronic equipment would to ~2% or less. Semiconductor sales for 2008 would only decrease about 3-7%, and the electronics manufacturing service sector’s growth could decrease 7-10%. Foundry revenue would shrink -5% to -10%. After a multiyear expansion streak, semiconductor assembly and test services might not extend it into 2008. However, company revenues should fare relatively well year over year as integrated device manufacturers (IDMs) continue migrating to the back-end outsourcing model. Capital spending would decline about 15-20% in 2008. Capital equipment markets would have a decline of 14-18%. Materials markets would have slow unit expansion (low single digits) with enhanced price pressure.

The 4Q07 semiconductor forecast shows that the 2008 outlook continues to soften. (Source: Gartner Dataquest Inc.)

Lewis views integration as a key trend. “Chip counts per system are dropping dramatically as suppliers reduce system size, improve reliability, lower power consumption and cut system costs,” he said. “One integrated chip is used where four chips were on a PCB.” While worldwide ASIC design starts are dropping, this is deceiving. As Lewis put it, “People overlook that the average gate count per new design is rising faster than the rate of decline. We’re shipping more ASIC gates than ever before.” Gartner estimates the average gate count in the United States was ~6 million gates (logic plus memory) in 2006, and will reach ~7.3 million in 2007.

The increase in on-chip memory (SRAM, increasingly embedded DRAM, and some flash) is the main gate count driver. Annual gate count growth in the United States for 2007 should slightly exceed 20%, while design starts should decline about 6%. Leading-edge designs as a percentage of ASIC designs continue dropping because of high costs. Design costs for 65 nm and below ASIC designs could hit $30M.

Gartner estimates that 85% of design starts at 65 nm and below will originate from the United States and Japan. The United States leads in producing designs primarily for high-performance computing, wired communications, high-end storage, high-end cellphones and game consoles. Gartner estimates that only about 200 designs of 65 nm and below will be completed (tape-outs) worldwide in 2007; by 2010, only larger companies will work on leading-edge designs; OEMs will do fewer custom chips and there will be fewer suppliers to amortize leading-edge R&D manufacturing costs.