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Surface Finishes for Capital Equipment in Industrial Cleanroom Environments

Surface finishes have a significant impact on the cleanliness and static discharge compliance of capital equipment used in semiconductor fabs. This article reviews available and emerging techniques and materials for surface finishes.

Martin P. Aalund, Aquest Systems, Sunnyvale, Calif.; Karl Mathia, Renaissance Sciences Corp., Chandler, Ariz. -- Semiconductor International, 12/1/2007

The cleanliness compatibility of capital equipment used in industrial cleanroom facilities, such as semiconductor fabs, has become a critical factor in the business equation of IC and flat panel display (FPD) manufacturers.1,2 Increasingly complex cleanroom requirements, driven by ever-shrinking IC feature sizes and new materials, demand suitable surface finishes.

The choice of surface finish can influence product safety and yield through several effects, including electrostatic discharge and attraction (ESD/ESA) and airborne molecular contamination (AMC).3 Beyond these performance issues, there are economic factors related to cost, appearance and brand recognition. Industry standards control some of these evaluation and selection criteria.4 This article reviews both available and emerging techniques and materials, and compares several suitable solutions for typical cleanroom applications, including:

  • Mechanically polished stainless steel
  • Electrically polished stainless steel
  • Brushed stainless steel
  • Powder coat over steel and aluminum
  • Cold-rolled steel with liquid urethane paint
  • A hybrid solution with interior stainless steel and exterior powder coat

The six finishes are evaluated against specific selection criteria. For example, we found that in low volumes, the material costs are similar for all the finishes; for high volumes, however, a powder coat tends to have a cost advantage. Furthermore, there is evidence that stainless steel is a superior material with respect to AMC, ESD and ESA, but the emergence of dissipative powder coats that are fully compliant with SEMI E78 neutralizes the ESD advantage of stainless steel.5 Powder coat also offers many color offerings that can be used to influence tool appearance and promote the manufacturer's brand recognition.

In short, the technical advantages of some finishes are offset by the economic advantages of others. In fact, when weighing the results not only per common requirements, but also by their perceived values, the differentiation between these finishes become less significant. The best choice is often dependent on the application.

Surface finish options

Choosing the right finish and coating technology for a given application is not always straightforward. The decision must balance several factors, including cost, compliance with regulatory requirements, productivity, quality and customer requirements.

Mechanically polished stainless steel — Ground and polished to a near mirror finish. The resultant finish is chemically inert, conductive and excellent for AMC and particulate control.

Electropolished stainless steel — The work piece is immersed in a liquid media bath and subjected to direct current. The metal part is made anodic. Current flows from the anode to the cathode, removing metal ions. The bath chemistry, temperature, time and current density are controlled to produce a smooth, shiny coating that results in a crystalline metal surface with an attractive smoothness and luster. Unlike mechanical finishing systems, the electropolishing does not smear, bend, stress or fracture metal surfaces. However, the electrical process may leave chemical residue, which must be removed to prevent AMC. Overall, it has similar characteristics to mechanically polished stainless steel.

Brushed stainless steel — Provides a conductive surface and requires less effort to achieve the desired finish. The surface roughness can provide cavities and voids for particles to collect. Attention is needed to maintain a consistent brush-line appearance at corners and panel intersections. The appearance and AMC properties are generally inferior to polished stainless steel.

Powder coat — Powder coat is applied as dry powder. The coating is usually applied electrostatically and then cured with heat to allow it to flow and form a uniform coating. Unlike conventional liquid paint, powder coating does not require a solvent. The method can be applied to various materials, such as steel and aluminum, and generates superior coverage and durability compared with a standard painted application. Standard powder coat is not conductive.

Conductive/dissipative powder coat — The addition of carbon or other conductive elements results in a conductive powder coat material that provides a dissipative path to eliminate or limit charge buildup.

Cold-rolled steel with liquid urethane paint — Offers a low-cost alternative. It is a conventional liquid paint approach, and does not offer the same robustness or coverage as powder coat.

Some of the above surface finishes can be combined. For example, powder-coated exterior panels on a stainless frame, along with conductive interior stainless steel surfaces, would leverage the AMC, ESD and ESA advantages of stainless steel with the flexibility of powder coat. Anodized aluminum is also a technical alternative, but was not considered as a primary candidate because it suffers from high cost and low conductivity.

Evaluation, selection criteria

The huge cost and complexity of the transition from 200 to 300 mm wafers forced the industry to establish standards a priori, rather than post facto, to ensure their timely acceptance in the industry. Two standards organizations — I300I within Sematech (Austin, Texas) and J300 within Selete (Ibaraki, Japan) — are dedicated exclusively to 300 mm technology. The first set of standards established 10 years ago at SEMICON West 1997 defined interfaces and, thus, helped to spread adoption costs of the 300 mm transition across the industry. The continuously evolving IC manufacturing technologies, as well as shrinking linewidths and feature sizes, impact cleanliness requirements. Particle sizes that were acceptable at critical dimensions (CDs) of 1.0 μm are now considered "killer defects" as CDs shrink below 100 nm. The International Technology Roadmap for Semiconductors (ITRS) influences this trend with a timeline of technology nodes, including the expected introduction of new technologies, and the associated key requirements for particulate and environment control.6

Based on ITRS guidelines, 300 mm industry trends, applicable and emerging standards, and customer feedback, we established the criteria in Table 1. These criteria are ranked by their relative importance, which is the average obtained from three manufacturing sites — two in the United States and one in Europe. Table 1 shows that product safety is the biggest concern, with ESD/ESA and AMC at the No. 1 and 2 positions, respectively. Cost is the next criterion: manufacturing and material cost rank as No. 3 and 4, suggesting that the cost of ownership (CoO), which relates to product safety (yield and profitability), outranks purchase cost. Customer perception (appearance and brand recognition) rank 5 and 7, respectively. Tool weight is not a significant concern with tool manufacturers. The following text describes each of the requirements and provides quantitative data where available.

Selection criterion 1: Electrostatic charges — Electrostatic charges in semiconductor manufacturing tools pose a high risk to product safety and, as such, to wafer yield and profitability.7-9 This is because of two primary effects: ESD and ESA. ESD occurs when a charge differential, or voltage, between two objects is suddenly relieved. If a wafer is in the proximity of a charged object and the voltage exceeds the minimum dielectric breakdown strength of air, a rapid discharge of energy can occur.

This discharge can impact the manufacturing process in two ways. First, the discharged energy can cause tool malfunction or damage, leading to tool downtime while the system is reset or repaired.4 Second, an energy discharge to or from the wafer can cause device damage and, thus, reduced yield. ESD can also cause electromagnetic interference (EMI) and potentially impact the performance of electronic equipment, such as sensors, unshielded cables and communications systems.10

The dielectric breakdown strength (i.e., discharge voltage) of dry air at standard temperature and pressure (STP) is highly dependent on the electrode shape and size. At STP, the minimum is ~380 V. The STP is an international standard set of conditions for experimental measurements to enable comparisons between sets of data.11 The STP conditions are an absolute pressure of 100 kPa (1 bar) and a temperature of 273.15 K (0°C). Sematech guidelines recommend that all surfaces in a cleanroom, including tools and mini-environments, be static dissipative or conductive.12 Furthermore, static charges should not exceed ±150 V/cm when measured with a handheld meter. The recommended limit will be reduced to <50 V/cm at the 22 nm technology node (Fig. 1).13 The ITRS recommends that all surfaces within 30 cm of a product be dissipative to control and eliminate ESD.14

1. Sematech guidelines recommend limiting static charges in tools and mini-environments to <50 V/cm by 2016.

The ESA of particles is a physical effect in the proximity of charged surfaces and objects, where electrostatic fields create forces that attract particles. The rate at which particles are deposited on the product (substrate, wafer) depends on several factors: field strength, field divergence, particle size and particle charge. An accurate measurement of these parameters is difficult to achieve, so the implementation of good design practices is usually the recommended preventive measure.15,5 The deposition rate for particles obviously depends on the contamination level as well (i.e., the number of particles in the environment, and the time the product is exposed to the contaminated environment). We consider three control variables for minimizing the risk of ESA:

  • Electrostatic field strength
  • Exposure time
  • Contamination level (number of airborne particles)

Figure 2 shows the time a wafer can stay in a Class 1 environment without exceeding contamination limits based on the number of particles that it can have deposited. The three axes represent time, the electrical field strength and the charge ratio (i.e., the ratio between positive and negative ions that are present in the environment). This charge ratio can be controlled with an ionizer, which creates a deterministic charge ratio that ensures product safety.

2. The amount of time a wafer can stay in a Class 1 environment without exceeding contamination limits depends on charge ratio and field strength. An ionizer can lengthen this time by decreasing the charge ratio while controlling particle deposition.

A decreasing charge ratio within a tool allows an increasing exposure time for wafers while maintaining the same level of particle deposition. The contamination risk can be further mitigated with improved cleanliness and by minimizing the wafer exposure time (e.g., with sophisticated automation). Conductive or dissipative surfaces are key for meeting new and emerging ESD requirements. Stainless steel has the advantage of being conductive, but dissipative powder coats and urethane paint are now available as well. Ionizers can be used to control both ESD and ESA: A known charge ratio is obtained by flooding an enclosed environment (tool, equipment front-end module [EFEM], etc.) with a quantity of both positive and negative ions.

Selection criterion 2: Airborne molecular contamination — With feature sizes shrinking below 0.1 µm, the prevention of AMC using particulate control measures and by careful materials selection is critical. The ITRS promotes tightening cleanliness standards — a continuously decreasing critical particle size and tightening limits for the number of particles contaminating the wafer surface.3,16 Particle deposition on a wafer depends on a variety of conditions, including:

  • Particulates in the vicinity of wafers
  • Airborne molecular contamination
  • Wafer handling (backside or edge gripping)
  • ESA
  • Exposure time of wafer in uncontrolled environment

Shorter exposure times and eliminating contaminants are key for controlling AMC. Automation is one means to limit wafer exposure. Other options are new materials and enhanced environmental control to prevent particulates from entering the wafer's proximity. Figure 3 shows ITRS guidelines for critical particle sizes. It also emphasizes today's limit of 30 nm defect size for commercially available detection sensitivity. This critical particle size is ~50% of the feature size of the devices manufactured on the wafer.

3. ITRS guidelines for wafer environmental contamination control show ever-decreasing limits for critical particle sizes. Commercial metrology tools are currently limited to a detection sensitivity of 30 nm defects.

Selection criterion 3: Cost of materials and manufacturing — Cost is a major factor in the semiconductor business equation. Here, the relative costs of materials and manufacturing are combined and compared with the other criteria. Table 2 lists the cost for three typical, United States-made parts in the $600 price range, and an assembly in the $6000 price range manufactured in Germany. The cost impact of both exterior finish and quantity is listed. The cost of a polished stainless steel finish is used as the 100% reference point. Mirror-polished stainless steel is among the most expensive finishes, independent from part size or manufacturing location. The materials and manufacturing costs, including labor, vary by region, and are also influenced by in-house capabilities of manufacturers.

Selection criterion 4: Brand recognition — The promotional objective of brand recognition is to distinguish a product from competitive alternatives in the applicable markets. For example, an EFEM is often the only part of a production or metrology tool visible to personnel and visitors on the factory floor. A surface finish that can support brand recognition is therefore desirable for the EFEM exterior.

Selection criterion 5: Cost of materials — The cost of materials and manufacturing are merged under Selection criterion 3.

Selection criterion 6: Appearance — The appearance of a tool to prospective customers is significant, and influences the selection of a surface finish for visible parts of a cleanroom tool. This includes both the appearance at delivery and as the tool ages. This has motivated factories to specify mirror finishes or specific colors for external surfaces.

Selection criterion 7: Weight of tool — The overall weight of a tool can impact costs in several ways, including cost of manufacturing, shipping, tool installation and start-up, and seismic constraints. This criterion was not found to be significant for finish selection.

Data analysis, ranking

Our objective was to establish ranked selection criteria for surface finishes in cleanroom environments. First-hand data about the perceived importance of surface finishes with respect to the above selection criteria were obtained through a survey of EFEM manufacturers. Key personnel were interviewed about preferences for internal and external surfaces, as well as the reasons for the decision. The interviewees were asked to first numerically prioritize the selection criteria, and then to rank the surface finishes with respect to the prioritized selection criteria. This data was then combined with publicly available data and literature.

EFEMs were selected for the survey because they provide a controlled sample set, are governed by SEMI standards, are widely used in the industry, and are provided by a broad range of suppliers. They are used for the automated wafer transport from FOUPs to process and metrology tools. EFEMs also separate exposed wafers from the ambient factory environment (i.e., reduce human interactions with).12,17 As a result, EFEMs have become complex systems for automated material handling and tight environmental control, and will continue to increase in complexity with more demanding cleanliness requirements and shrinking feature sizes.

We expect future EFEMs to include additional data collection and analysis for wafer safety. Environmental control was once limited to particulate control, but not anymore. Temperature, airflow, pressure, humidity, AMC and static charge control are also considered environmental parameters of interest. The analysis and selection of appropriate surface finishes that are compatible with applicable environmental requirements must be part of product designs for cleanroom facilities.

Each interviewed manufacturer has a preferred finish and different product mix, so the raw data was weighted with the relative importance among the selection criteria. Finish options were ranked with a value from 1 to 10 for each of the selection criteria, with 10 being the most desirable. Table 3 lists the averaged raw data without weighting. The raw data shows mechanically polished stainless steel as the No. 1 finish option with a value of 7.78, followed closely by the hybrid solution and powder coat.

The finish rankings Ri, i=1.7, in Table 3 were then multiplied with the relative importance I rel of the selection criteria listed in Table 1. That is, I rel was used as the weighting factors for each selection criterion, and each finish preference in Table 3 was multiplied by the associated I rel, then summed and normalized to a value of 1 for each finish:

4. Adding relative importance to the averaged raw data in Table 3 still puts mechanically polished stainless steel in first place for surface finishes.
The result is shown in Figure 4. The weighted ranking shows mechanically polished stainless steel in first place, but closely followed by powder coat and hybrid solutions. Note that this order was obtained using both the raw and weighted data. Brushed stainless steel came in last in both cases.

Conclusions

Several suitable surface finishes were evaluated and compared using different technical and economic selection criteria. It was found that technical advantages of some materials are offset by the economic advantages of others, and that the best choice is often application-dependent.

The case study showed that little differentiation exists in the perceived value between stainless steel and powder coat. Stainless is a superior technical solution with respect to AMC, ESD and ESA, while powder coat has a cost advantage in high volumes. The emergence of new dissipative powder coats with low AMC and outgassing will add attractive alternatives in terms of cost and technical properties.



Author Information
Martin P. Aalund is vice president of engineering and product development at Aquest Systems Inc. His career in automation spans both industry and academia. He has led the development of numerous automation systems for the global semiconductor and pharmaceutical automation industries, and has several patents in the areas of vacuum and atmospheric robotics. He holds a Ph.D. in mechanical engineering from the University of Texas at Austin.
Karl Mathia is principal investigator and program manager at Renaissance Sciences Corp. He has 20 years of experience in product development and applied research, and has published extensively in the area of robotics and automation. He holds M.S. and Ph.D. degrees in electrical engineering.


References
  1. M. Misuris, "Environmental Controls: Challenges and Approaches for Toolmakers," CleanRooms, July 2002, p. S3.
  2. J. Menear and A. Steinman, "Certifying Process Equipment and Mini-Environments With SEMI E78-0998," Compliance Engineering, 2000 Reference Guide.
  3. "Forecast of Airborne Molecular Contamination Limits for the 0.25 Micron High Performance Logic Process," International Sematech, Technology Transfer 95052812A-TR, May 31, 1995.
  4. SEMI E10, Standard of Definition and Measurement of Equipment Reliability, Availability and Maintainability (RAM).
  5. SEMI E78-0998, Electrostatic Compatibility — Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment.
  6. International Technology Roadmap for Semiconductors (ITRS) 2006. Available at: www.itrs.net.
  7. L.B. Levit, L.G. Henry, J.A. Montoya, F.A. Marcelli and R.P. Lucero, "Investigating FOUPs as a Source of ESD-Induced Electromagnetic Interference," Micro, April 2002, p. 41.
  8. L.B. Levit, T.M. Hanley and F. Curran, "In 300mm Contamination Control, Watch Out for Electrostatic Attraction," Solid State Technology, June 2000.
  9. D.W. Cooper, R.P. Donovan and A. Steinman, "Controlling Electrostatic Attraction of Particles in Production Equipment," Semiconductor International, July 1999, p. 149.
  10. SEMI E33-94, Specification for Semiconductor Manufacturing Facility Electromagnetic Compatibility.
  11. "Compendium of Terminology," 2nd Edition, 1997, IUPAC Secretariat (International Union of Pure and Applied Chemistry), Research Triangle Park, N.C. (former and present definitions) IUPAC Compendium.
  12. "Integrated Mini-Environment Design Best Practices," International Sematech, Technology Transfer No. 99033693A-ENG, March 31, 1999.
  13. ITRS 2001, Factory Integration Chapter, Electrostatic Discharge-Backup.
  14. ITRS 2001, Factory Integration Chapter, Static Charge Control-Backup.
  15. SEMI E43, Recommended Practice for Measuring Static Charge on Objects and Surfaces.
  16. SEMI F21-95, Classification of Airborne Molecular Contaminant Levels in Clean Environments.
  17. SEMI E101-1000, Provisional Guide for EFEM Functional Structure Model.
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